Estimating an error rate associated with memory
The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.
1. A method for operating memory, comprising:
sensing a first page of data stored in a group of memory cells;
determining a quantity of parity violations associated with a low-density parity-check (LDPC) operation performed on the sensed first page of data;
estimating an error rate on a memory die associated with the first page of data based on the determined quantity of parity violations;
determining whether the estimated error rate meets or exceeds a threshold; and
upon determining the estimated error rate meets or exceeds the threshold:
generating soft data from the group of memory cells to send to a controller coupled to the memory, prior to the controller requesting the soft data, to reduce latency in the controller receiving the soft data;
correcting, using the soft data, the sensed first page of data to reduce errors in the sensed first page of data prior to programming a second page of data; and
programming the first page of data with the reduced errors and the second page of data to the group of memory cells using the corrected data.
2. The method of claim 1 , wherein the group of memory cells includes triple level memory cells.
3. The method of claim 1 , wherein the method includes programming the second page of data to the group of memory cells using the sensed first page of data upon determining the estimated error rate does not meet or exceed the threshold.
4. The method of claim 1 , wherein correcting the sensed first page of data includes:
sending the sensed first page of data to the controller coupled to the memory; and
correcting the sensed data using error correction circuitry located on the controller.
5. The method of claim 1 , wherein the first page is a lower page of data and the second page is an upper page of data.
6. The method of claim 1 , wherein the threshold is based on an error correction capability of a controller coupled to the memory.
7. The method of claim 1 , wherein the LDPC operation is performed on the sensed first page of data by:
interleaving the sensed first page of data into a number of data segments; and
performing an XOR operation on each of the data segments.
8. The method of claim 1 , wherein the method includes estimating the error rate associated with the first page of data by dividing the determined quantity of parity violations by an amount of data stored in the first page of data.
9. An apparatus, comprising:
a memory; and
circuitry configured to:
sense a first page of data stored in a group of memory cells in the memory;
determine a quantity of parity violations associated with a low-density parity check (LDPC) operation performed on the sensed first page of data;
estimate an error rate associated on a memory die with the first page of data based on the determined quantity of parity violations;
determine whether the estimated error rate meets or exceeds a threshold; and
upon determining the estimated error rate meets or exceeds the threshold:
generate soft data from the group of memory cells to send to a controller coupled to the memory, prior to the controller requesting the soft data, to reduce latency in the controller receiving the soft data;
correct, using the soft data, the sensed first page of data to reduce errors in the sensed first page of data prior to programming a second page of data; and
program the first page of data with the reduced errors and the second page of data to the group of memory cells using the corrected data.