Estimating an error rate associated with memory
The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.
1. A method for operating memory, comprising:
sensing data stored in a memory;
performing an error detection operation on the sensed data, wherein performing the error detection operation on the sensed data includes:
interleaving the sensed data into a number of data segments; and
performing an XOR operation on each of the data segments;
determining a quantity of parity violations associated with the error detection operation; and
estimating an error rate associated with the memory based on the determined quantity of parity violations.
2. The method of claim 1 , wherein the method includes:
performing the error detection operation using circuitry in the memory;
determining the quantity of parity violations using the circuitry in the memory; and
estimating the error rate associated with the memory using the circuitry in the memory.
3. The method of claim 1 , wherein the method includes:
determining whether the estimated error rate associated with the memory meets or exceeds a threshold; and
correcting the sensed data upon determining the estimated error rate meets or exceeds the threshold.
4. The method of claim 3 , wherein the method includes not correcting the sensed data upon determining the estimated error rate does not meet or exceed the threshold.
5. The method of claim 1 , wherein the method includes:
determining whether the estimated error rate associated with the memory meets or exceeds a threshold; and
including an option to generate soft data associated with the sensed data upon determining the estimated error rate meets or exceeds the threshold.
6. The method of claim 1 , wherein the error detection operation is a low-density parity check operation using low-density parity check code parities.
7. The method of claim 1 , wherein determining the quantity of parity violations associated with the error detection operation includes summing the quantity of parity violations that occur during the XOR operations.
8. An apparatus, comprising:
a memory; and
circuitry configured to:
sense data stored in the memory;
perform an error detection operation on the sensed data, wherein performing the error detection operation on the sensed data includes:
interleaving the sensed data into a number of data segments; and
performing an XOR operation on each of the data segments;
determine a quantity of parity violations associated with the error detection operation performed on the sensed data; and
estimate an error rate associated with the memory based on the determined quantity of parity violations.
9. The apparatus of claim 8 , wherein the memory and the circuitry are included on a same die.
10. The apparatus of claim 8 , wherein:
the apparatus includes a controller coupled to the memory; and
the controller includes the circuitry.
11. The apparatus of claim 8 , wherein the circuitry is configured to estimate the error rate associated with the memory by:
dividing the determined quantity of parity violations by the amount of data on which the error detection operation is performed; and
multiplying the division result by a scalar.
12. The apparatus of claim 11 , wherein the scalar is based on the determined quantity of parity violations.
13. The apparatus of claim 11 , wherein the scalar is a fixed value.