Block or page lock features in serial interface memory

1. A memory device comprising:

a memory array;

a serial interface controller comprising an input, wherein the serial interface is configured to interface with a master device via the input to receive a request to access a portion of the memory array from the master device and a password from the master device; and

a register separate from and directly coupled to the serial interface controller via a data line, wherein the register is configured to enable or disable write or erase access to the portion of the memory array based upon data received indicating whether to enable or disable access to the portion that is written into the register via the input and the data line if the password is validated via comparison of the password written into a second register via the input and the data line with a stored value of the password, wherein the portion of the memory array is configured to store an indication of the data written into the register, wherein the serial interface controller is configured to initiate a read access of the portion of the memory array subsequent to receipt of a read command if the password is validated via comparison of the password written into a second register with the stored value of the password.

2. The memory device of claim 1 , wherein the data indicating whether to enable or disable access to the portion is configured to be written into the register via the serial interface controller with a command accompanied by an address identifying the portion, wherein the command, the address, and the data are serially received by the serial interface controller.

3. The memory device of claim 1 , wherein the register is configured to enable or disable write or erase access to the portion comprises the register being configured to lock or unlock write access to the portion.

4. The memory device of claim 1 , wherein the register is configured to enable or disable write or erase access to the portion comprises the register being configured to lock or unlock erase access to the portion.

5. The memory device of claim 1 , wherein the portion comprises an individual area of the memory array.

6. The memory device of claim 5 , wherein the individual area of the memory array comprises a boot area.

7. The memory device of claim 1 , wherein the portion comprises an individual page within a particular block of the memory array.

8. The memory device of claim 1 , wherein the portion comprises a block region comprising one or more blocks of the memory array.

9. The memory device of claim 8 , wherein the block region is user-definable.

10. The memory device of claim 8 , wherein the block region comprises an entire boot area.

11. The memory device of claim 1 , wherein the portion comprises a block region comprises a plurality of blocks.

12. The memory device of claim 1 , wherein the register comprises a plurality of bits and wherein the portion is associated with a particular bit of the plurality of bits.

13. The memory device of claim 1 , wherein the serial interface controller comprises a serial data in (SI) input as the input, a serial data out (SO) output, a serial clock (SCK) input, and a chip select (CS) input.

14. The memory device of claim 1 , comprising a cache memory coupled to the controller by way of a first line, wherein the controller is coupled to the memory array by way of a second line and the cache memory is coupled to the memory array by way of a third line.

15. The memory device of claim 1 , wherein the controller is configured to translate signals sent to the memory array into command latch enable (CLE), address latch enable (ALE) signal, write enable (WE), and read enable (RE) signals.

16. The memory device of claim 1 , wherein the memory device is configured to track a number of unsuccessful attempts in which the master device attempts to access the portion of the memory array and prevents further accesses to the portion of the memory array when the number of unsuccessful attempts reaches a threshold value.

17. The memory device of claim 1 , wherein the memory device is configured to authenticate the master device for accessing the memory array responsive to comparing the password entered by the master device to a stored password to validate the password.

18. The memory device of claim 17 , wherein the stored password is stored in the memory array.

19. The memory device of claim 1 , wherein the register comprises a boot access register.

20. A system comprising:

a master device configured to transmit a password; and

a memory device coupled to the master device, the memory device comprising:

a memory array;

a serial interface controller comprising an input, wherein the serial interface is configured to interface with the master device via the input to receive a request to access a portion of the memory array from the master device and a password from the master device; and

a register separate from and directly coupled to the serial interface controller via a data line and configured to enable or disable write or erase access to the portion of the memory array responsive to a command addressing the portion and data indicating whether to enable or disable access to the portion, wherein the data is written into the register via the input and the data line if the password is validated at the memory device via comparison of the password written into a second register via the input and the data line with a stored value of the password, wherein the portion of the memory array is configured to store an indication of the data written into the register, wherein the serial interface controller is configured to initiate a read access of the portion of the memory array subsequent to receipt of a read command if the password is validated via comparison of the password written into a second register with the stored value of the password.

21. The system of claim 20 , wherein the master device comprises programmed control circuitry.

22. The system of claim 21 , wherein the programmed control circuitry comprises a microcontroller.

23. A method, comprising:

receiving a password from a host device at an input of a serial interface controller;

evaluating the password to determine whether the password is validated via comparison of the password written into a register via the input and a data line directly coupling the serial interface controller to the register with a stored value of the password;

receiving a request to access a portion of a memory array from the host device at the input of the serial interface controller;

writing a first value to a memory access register via the data line directly coupling the serial interface controller to the memory access register to disable an access lock value of the memory access register based upon the received request from the host device being a write or erase access if the password is validated, wherein the access lock value, when enabled, prevents write or erase access to the portion of the memory array;

writing a second value to a memory array to disable a write lock value of the memory array if the access lock value is disabled;

accessing a portion of the memory array if the write lock value is disabled; and

reading a value from the portion of the memory array based upon the received request from the host device being a read access if the password is validated.