Apparatus including gettering agents in memory charge storage structures
Apparatus having a processor and a memory device in communication with the processor, the memory device including an array of memory cells and a control logic to control access of the array of memory cells, wherein the array of memory cells includes a memory cell having a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, and wherein the charge storage structure includes a charge-storage material and a gettering agent.
1. An apparatus, comprising:
a processor; and
a memory device in communication with the processor, the memory device comprising:
an array of memory cells; and
a control logic to control access of the array of memory cells, wherein the array of memory cells comprises a memory cell comprising:
a first dielectric adjacent a semiconductor;
a control gate;
a second dielectric between the control gate and the first dielectric; and
a charge storage structure between the first dielectric and the second dielectric;
wherein the charge storage structure comprises a charge-storage material and a gettering agent; and
wherein at least a portion of the charge storage structure comprises a ratio of the gettering agent to the charge-storage material that is greater than a stoichiometric amount.
2. The apparatus of claim 1 , wherein, in the memory cell, the charge-storage material is a silicon-containing material.
3. The apparatus of claim 1 , wherein, in the memory cell, the gettering agent comprises a plurality of gettering agents.
4. The apparatus of claim 1 , wherein, in the memory cell, the gettering agent comprises an element or compound meeting at least one criteria, under process conditions experienced by the charge-storage material, selected from a group consisting of preferentially reacting with unreacted oxygen over the charge-storage material, pulling reacted oxygen away from an oxidized charge-storage material, further reacting with oxidized charge-storage material to produce a compound that is conductive, and further reacting with oxidized charge-storage material to produce a dielectric compound that has a higher k value than the oxidized charge-storage material.
5. The apparatus of claim 1 , wherein, in the memory cell, the gettering agent comprises a metal.
6. The apparatus of claim 5 , wherein, in the memory cell, the metal is selected from a group consisting of zirconium, beryllium, magnesium, calcium, strontium, scandium, yttrium, rare earth metals, lanthanum, thorium, uranium, hafnium, aluminum and titanium.
7. The apparatus of claim 5 , wherein, in the memory cell, the gettering agent comprises a silicide of the metal.
8. The apparatus of claim 1 , wherein, in the memory cell, at least a portion of the gettering agent is incorporated into the charge-storage material.
9. The apparatus of claim 8 , wherein, in the memory cell, the gettering agent is incorporated into only a portion of the charge-storage material.
10. The apparatus of claim 1 , wherein, in the memory cell, a concentration of the gettering agent is greater nearer the second dielectric than a concentration of the gettering agent nearer the first dielectric.
11. The apparatus of claim 1 , wherein, in the memory cell, the charge-storage material is devoid of the gettering agent in a portion nearer the first dielectric.
12. The apparatus of claim 1 , wherein the memory device of the apparatus further comprises:
an address register for latching address signals received from the processor;
a command register for latching command signals received from the processor;
a row decode circuitry for decoding the address signals latched in the address register; and
a column decode circuitry for decoding the address signals latched in the address register;
wherein the control logic of the memory device is configured to control access of the array of memory cells in response to the command signals latched in the command register, and is further configured to control the row decode circuitry and the column decode circuitry in response to the address signals latched in the address register for access of the array of memory cells.
13. An apparatus, comprising:
a processor; and
a memory device in communication with the processor, the memory device comprising:
an array of memory cells; and
a control logic to control access of the array of memory cells, wherein the array of memory cells comprises a memory cell comprising:
a first dielectric adjacent a semiconductor;
a control gate;
a second dielectric between the control gate and the first dielectric; and
a charge storage structure between the first dielectric and the second dielectric;
wherein the charge storage structure comprises a silicon-containing material and a metal; and
wherein at least a portion of the charge storage structure comprises a ratio of the metal to the silicon-containing material that is greater than a stoichiometric amount.
14. The apparatus of claim 13 , wherein the memory device of the apparatus further comprises:
an address register for storing an address received from the processor; and
a command register for storing a command received from the processor;
wherein the control logic of the memory device is configured to control access of the array of memory cells in response to the command stored in the command register and the address stored in the address register.
15. The apparatus of claim 13 , wherein, in the memory cell, the charge storage structure comprises the silicon-containing material and one or more metals.
16. The apparatus of claim 15 , wherein, in the memory cell, a concentration of the one or more metals is greater than or equal to 1E19/cm 3 .
17. The apparatus of claim 16 , wherein, in the memory cell, the concentration of the one or more metals is greater than 50 atomic percent.
18. An apparatus, comprising:
a processor; and
a memory device in communication with the processor, the memory device comprising:
an array of memory cells; and
a control logic to control access of the array of memory cells, wherein the array of memory cells comprises a memory cell comprising:
a first dielectric adjacent a semiconductor;
a control gate;
a second dielectric between the control gate and the first dielectric; and
a charge storage structure between the first dielectric and the second dielectric;
wherein the charge storage structure comprises polysilicon and a metal silicide; and
wherein the charge storage structure further comprises an unreacted elemental metal incorporated therein.
19. The apparatus of claim 18 , wherein, in the memory cell, no portion of the polysilicon is in contact with the second dielectric.
20. The apparatus of claim 18 , wherein the memory device of the apparatus further comprises:
an input/output (I/O) control circuitry;
an I/O bus for communication of command signals, address signals and/or data signals from the processor to the I/O control circuitry; and
a control link between the processor and the control logic for communication of control signals from the processor to the control logic.
21. An apparatus, comprising:
a processor; and
a memory device in communication with the processor, the memory device comprising:
an array of memory cells; and
a control logic to control access of the array of memory cells, wherein the array of memory cells comprises a memory cell comprising:
a first dielectric adjacent a semiconductor;
a control gate;
a second dielectric between the control gate and the first dielectric; and
a charge storage structure between the first dielectric and the second dielectric;
wherein the charge storage structure consists essentially of metal silicon oxide and at least one component selected from a group consisting of a metal silicide, a metal oxide and an unreacted metal; and
wherein at least a portion of the at least one component is incorporated into the silicon-containing material.
22. An apparatus, comprising:
a processor; and
a memory device in communication with the processor, the memory device comprising:
an array of memory cells; and
a control logic to control access of the array of memory cells, wherein the array of memory cells comprises a memory cell comprising:
a first dielectric adjacent a semiconductor;
a control gate;
a second dielectric between the control gate and the first dielectric; and
a charge storage structure between the first dielectric and the second dielectric;
wherein the charge storage structure consists essentially of a metal silicide and at least one component selected from a group consisting of a metal silicon oxide, a metal oxide and an unreacted metal; and
wherein at least a portion of the at least one component is incorporated into the metal silicide.
23. An apparatus, comprising:
a processor; and
a memory device in communication with the processor, the memory device comprising:
an array of memory cells; and
a control logic to control access of the array of memory cells, wherein the array of memory cells comprises a memory cell comprising:
a first dielectric adjacent a semiconductor;
a control gate;
a second dielectric between the control gate and the first dielectric; and
a charge storage structure between the first dielectric and the second dielectric;
wherein the charge storage structure comprises a charge-storage material, a reaction product of a metal and the charge-storage material, and unreacted instances of the metal.
24. The apparatus of claim 23 , wherein, in the memory cell, the charge storage structure further comprises:
a first instance of the charge-storage material;
a second instance of the charge-storage material between the first instance of the charge-storage material and the second dielectric;
a first instance of the reaction product of the metal and the charge-storage material between the first instance of the charge-storage material and the second instance of the charge-storage material;
a second instance of the reaction product of the metal and the charge-storage material between the second instance of the charge-storage material and the second dielectric;
a first unreacted instance of the metal between the first instance of the reaction product of the metal and the charge-storage material, and the second instance of the charge-storage material; and
a second unreacted instance of the metal between the second instance of the reaction product of the metal and the charge-storage material, and the second dielectric.
25. The apparatus of claim 24 , wherein, in the memory cell, the second instance of the charge-storage material is thinner than the first instance of the charge-storage material, and wherein the second unreacted instance of the metal is thicker than the first unreacted instance of the metal.
26. The apparatus of claim 24 , wherein, in the memory cell, the second instance of the charge-storage material is thinner than the first instance of the charge-storage material, and wherein the second unreacted instance of the metal and the first unreacted instance of the metal are a same thickness.
27. The apparatus of claim 24 , wherein, in the memory cell, the second instance of the charge-storage material and the first instance of the charge-storage material are a same thickness, and wherein the second unreacted instance of the metal is thicker than the first unreacted instance of the metal.
28. The apparatus of claim 24 , wherein the memory device of the apparatus further comprises:
an address register for storing an address received from the processor; and
a command register for storing a command received from the processor;
wherein the control logic of the memory device is configured to control access of the array of memory cells in response to the command stored in the command register and the address stored in the address register.