IP Library Granted Patent US 8,748,964
Granted Patent B2
US 8,748,964 · App. 12/910,404 · Granted Jun 10, 2014

Gettering agents in memory charge storage structures

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Quick Facts
Patent No.
US 8,748,964
App. No.
12/910,404
Granted
Jun 10, 2014
Kind
B2
Abstract

Memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.

Claims (67)

1. A memory cell, comprising:

a first dielectric over a semiconductor;

a charge storage structure over the first dielectric;

a second dielectric over the charge storage structure;

a control gate over the second dielectric; and

source/drain regions in the semiconductor generally adjacent the first dielectric;

wherein the charge storage structure comprises a charge-storage material and a gettering agent; and

wherein at least a portion of the charge storage structure comprises a ratio of the gettering agent to the charge-storage material that is greater than a stoichiometric amount.

2. The memory cell of claim 1 , wherein the charge-storage material is a silicon-containing material.

3. The memory cell of claim 2 , wherein the silicon-containing material is selected from the group consisting of amorphous silicon, monocrystalline silicon and polycrystalline silicon.

4. The memory cell of claim 1 , wherein the gettering agent comprises a plurality of gettering agents.

5. The memory cell of claim 1 , wherein the gettering agent comprises an oxygen gettering agent.

6. The memory cell of claim 1 , wherein the gettering agent comprises an element or compound meeting at least one criteria, under process conditions experienced by the charge-storage material, selected from the group consisting of preferentially reacting with unreacted oxygen over the charge-storage material, pulling reacted oxygen away from an oxidized charge-storage material, further reacting with oxidized charge-storage material to produce a compound that is conductive, and further reacting with oxidized charge-storage material to produce a dielectric compound that has a higher k value than the oxidized charge-storage material.

7. The memory cell of claim 1 , wherein the gettering agent comprises a metal.

8. The memory cell of claim 7 , wherein the metal is selected from the group consisting of zirconium, beryllium and magnesium.

9. The memory cell of claim 7 , wherein the metal is selected from the group consisting of zirconium, beryllium, magnesium, calcium, strontium, scandium, yttrium, rare earth metals, lanthanum, thorium, uranium, hafnium and aluminum.

10. The memory cell of claim 7 , wherein the metal is selected from the group consisting of zirconium, beryllium, magnesium, calcium, strontium, scandium, yttrium, rare earth metals, lanthanum, thorium, uranium, hafnium, aluminum and titanium.

11. The memory cell of claim 7 , wherein the gettering agent comprises a silicide of the metal.

12. The memory cell of claim 1 , wherein at least a portion of the gettering agent is incorporated into the charge-storage material.

13. The memory cell of claim 12 , wherein the gettering agent is incorporated into only a portion of the charge-storage material.

14. The memory cell of claim 1 , wherein the gettering agent is on the charge-storage material and separates the charge-storage material from the second dielectric.

15. The memory cell of claim 1 , wherein a concentration of the gettering agent is greater nearer the second dielectric than a concentration of the gettering agent nearer the first dielectric.

16. The memory cell of claim 1 , wherein the charge-storage material is devoid of the gettering agent in a portion nearer the first dielectric.

17. A memory cell, comprising:

a first dielectric over a semiconductor;

a charge storage structure over the first dielectric;

a second dielectric over the charge storage structure;

a control gate over the second dielectric; and

source/drain regions in the semiconductor generally adjacent the first dielectric;

wherein the charge storage structure comprises a silicon-containing material and a metal;

wherein at least a portion of the charge storage structure comprises a ratio of the metal to the silicon-containing material that is greater than a stoichiometric amount.

18. The memory cell of claim 17 , wherein the charge storage structure comprises a silicon-containing material and one or more metals.

19. The memory cell of claim 18 , wherein a concentration of the one or more metals is greater than or equal to 1E19/cm 3 .

20. The memory cell of claim 19 , wherein the concentration is greater than 50 atomic percent.

21. A memory cell, comprising:

a first dielectric over a semiconductor;

a charge storage structure over the first dielectric;

an second dielectric over the charge storage structure;

a control gate over the second dielectric; and

source/drain regions in the semiconductor generally adjacent the first dielectric;

wherein the charge storage structure comprises polysilicon and a metal silicide; and

wherein the charge storage structure further comprises an elemental metal incorporated therein.

22. The memory cell of claim 21 , wherein at least a portion of the metal silicide is incorporated into the polysilicon.

23. The memory cell of claim 21 , wherein the metal silicide separates the polysilicon from the second dielectric.

24. A memory cell, comprising:

a first dielectric over a semiconductor;

a charge storage structure over the first dielectric;

a second dielectric over the charge storage structure;

a control gate over the second dielectric; and

source/drain regions in the semiconductor generally adjacent the first dielectric;

wherein the charge storage structure consists essentially of a silicon-containing material and at least one component selected from the group consisting of a metal silicon oxide, a metal silicide, a metal oxide and a metal; and

wherein at least a portion of the at least one component is incorporated into the silicon-containing material.

25. The memory cell of claim 24 , wherein the at least one component separates the silicon-containing material from the second dielectric.

26. A memory cell, comprising:

a first dielectric over a semiconductor;

a charge storage structure over the first dielectric;

a second dielectric over the charge storage structure;

a control gate over the second dielectric; and

source/drain regions in the semiconductor generally adjacent the first dielectric;

wherein the charge storage structure consists essentially of a metal silicon oxide and at least one component selected from the group consisting of a metal silicide, a metal oxide and a metal.

27. A memory cell, comprising:

a first dielectric over a semiconductor;

a charge storage structure over the first dielectric;

a second dielectric over the charge storage structure;

a control gate over the second dielectric; and

source/drain regions in the semiconductor generally adjacent the first dielectric;

wherein the charge storage structure consists essentially of a metal silicide and at least one component selected from the group consisting of a metal silicon oxide, a metal oxide and a metal.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2010
From: BREWER, RHETT; RAMASWAMY, DURAI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 025183/0230 →