IP Library Granted Patent US 9,105,665
Granted Patent B2
US 9,105,665 · App. 14/290,215 · Granted Aug 11, 2015

Gettering agents in memory charge storage structures

Inventors: Rhett T. Brewer (Santa Clara, CA); Durai V. Ramaswamy (Boise, ID)
Assignee: Micron Technology, Inc.
H01L29/66825H01L21/28273H01L21/44H01L27/11521H01L29/42332H01L29/511H01L29/66833H01L29/7881H01L21/244H01L21/265
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Quick Facts
Patent No.
US 9,105,665
App. No.
14/290,215
Granted
Aug 11, 2015
Kind
B2
Abstract

Methods of forming memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.

Claims (60)

1. A method of forming a memory cell, comprising:

forming a first dielectric over a semiconductor;

forming a charge storage structure over the first dielectric;

forming a second dielectric over the charge storage structure;

forming a control gate over the second dielectric; and

forming source/drain regions in the semiconductor generally adjacent the first dielectric;

wherein forming the charge storage structure comprises:

forming a charge-storage material; and

incorporating a gettering agent into the charge storage structure at more than a stoichiometric amount.

2. The method of claim 1 , wherein incorporating a gettering agent into the charge storage structure comprises incorporating the gettering agents using a process selected from the group consisting of ionic implantation, sputtering, plasma, and chemical vapor deposition.

3. The method of claim 1 , wherein the gettering agent comprises an oxygen gettering agent.

4. The method of claim 1 , wherein forming a charge storage structure comprises forming a charge storage structure that has a conductivity selected from the group consisting of semiconductive and conductive.

5. A method of forming a memory cell, comprising:

forming a first dielectric over a semiconductor;

forming a charge storage structure over the first dielectric;

forming a second dielectric over the charge storage structure;

forming a control gate over the second dielectric; and

forming source/drain regions in the semiconductor generally adjacent the first dielectric;

wherein forming the charge storage structure comprises:

forming a charge-storage material; and

incorporating a gettering agent into the charge-storage material comprising implanting the gettering agent into the charge-storage material.

6. The method of claim 5 , wherein incorporating the gettering agent into the charge-storage material comprises incorporating the gettering agent into only a portion of the charge-storage material.

7. The method of claim 1 , wherein incorporating a gettering agent into the charge storage structure comprises forming the gettering agent on top of the charge-storage material.

8. The method of claim 1 , wherein incorporating a gettering agent into the charge storage structure comprises incorporating the gettering agent to have a concentration of the gettering agent near an interface of the charge storage structure and the second dielectric that is higher than a concentration of the gettering agent near an interface of the charge storage structure and the first dielectric.

9. A method of forming a memory cell, comprising:

forming a first dielectric over a semiconductor;

forming a silicon-containing material over the first dielectric;

incorporating a metal into the silicon-containing material;

annealing to react at least a portion of the metal with the silicon-containing material, thereby defining a charge storage structure;

forming a second dielectric over the charge storage structure;

forming a control gate over the second dielectric; and

forming source/drain regions in the semiconductor generally adjacent the first dielectric.

10. The method of claim 9 , wherein incorporating a metal into the silicon-containing material comprises incorporating a sufficient amount of the metal such that unreacted metal remains in the charge storage structure after annealing to react the at least a portion of the metal with the silicon-containing material.

11. The method of claim 9 , wherein annealing to react at least a portion of the metal with the silicon-containing material comprises forming at least one compound selected from the group consisting of a metal silicon oxide, a metal silicide and a metal oxide.

12. The method of claim 9 , wherein the silicon-containing material contains a silicon oxide and further comprising reacting the at least a portion of the metal with the silicon-containing material to convert at least a portion of the silicon oxide to a metal silicon oxide, or silicon and a metal oxide.

13. The method of claim 9 , wherein the silicon-containing material contains a silicon oxide and further comprising reacting the at least a portion of the metal with the silicon-containing material to convert at least a portion of the silicon oxide to a compound that is either conductive or has a dielectric constant greater than a dielectric constant of silicon dioxide.

14. The method of claim 9 , further comprising:

preferentially reacting oxygen with at least a further portion of the metal over the silicon-containing material.

15. The method of claim 9 , wherein reaction products from annealing to react at least a portion of the metal with the silicon-containing material separate remaining portions of the silicon-containing material from the second dielectric.

16. A method of forming a memory cell, comprising:

forming a first dielectric over a semiconductor;

forming an instance of charge-storage material over the first dielectric;

forming an instance of metal, wherein the instance of metal is formed over the instance of charge-storage material;

reacting the instance of charge-storage material with only a portion of the instance of metal, thereby defining a charge storage structure containing an unreacted portion of the instance of metal;

forming a second dielectric over the charge storage structure;

forming a control gate over the second dielectric; and

forming source/drain regions in the semiconductor generally adjacent the first dielectric.

17. The method of claim 16 , wherein reacting the instance of charge-storage material with the at least a portion of the instance of metal occurs during or after forming the second dielectric.

18. A method of forming a memory cell, comprising:

forming a first dielectric over a semiconductor;

forming two or more instances of charge-storage material over the first dielectric;

forming two or more instances of metal, wherein each instance of metal is formed over a corresponding instance of charge-storage material;

reacting each instance of charge-storage material with at least a portion of its corresponding instance of metal, thereby defining a charge storage structure;

forming a second dielectric over the charge storage structure;

forming a control gate over the second dielectric; and

forming source/drain regions in the semiconductor generally adjacent the first dielectric.

19. The method of claim 18 , wherein each successive instance of charge-storage material is thinner than a prior instance of charge-storage material, while each successive instance of metal is thicker than a prior instance of metal.

20. The method of claim 18 , wherein each successive instance of charge-storage material is thinner than a prior instance of charge-storage material, while each instance of metal has a uniform thickness.

21. The method of claim 18 , wherein each successive instance of metal is thicker than a prior instance of metal, while each instance of charge-storage material has a uniform thickness.

22. The method of claim 5 , wherein implanting the gettering agent into the charge-storage material comprises implanting the gettering agent using a process selected from a group consisting of ionic implantation and plasma deposition.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 12910404 · Oct 22, 2010
Related Publication 20140264526A1 · Sep 18, 2014