Semiconductor with through-substrate interconnect
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.
1. A method of fabricating a semiconductor device comprising:
etching a via into a silicon substrate from a first side toward a second side of the silicon substrate;
forming a conductive interconnect in the etched via, the conductive interconnect having a first end proximate the first side of the silicon substrate and a second end proximate the second side of the silicon substrate;
insulating the conductive interconnect with a first dielectric material proximate the first side of the silicon substrate;
forming a first metal routing structure on the first dielectric material, the first metal routing structure being at least partially in the first dielectric material;
insulating the conductive interconnect and the first metal routing structure with a second dielectric material;
forming a plurality of openings in the second dielectric material, the openings including a first opening generally corresponding to the first metal routing structure, a second opening generally corresponding to the conductive interconnect, and a third opening generally corresponding to a second metal routing structure; and
filling the plurality of openings with a conductive material, thereby forming a first conductive path between the first and second metal routing structures, a second conductive path between the second metal routing structure and the conductive interconnect, and the second metal routing structure.
2. The method of claim 1 , further comprising:
forming an insulating material in the etched via;
forming a seed material on the insulating material;
blocking selected regions of the seed material located outside of the via with a photoresist; and
plating exposed regions of the seed material to fill the via with a conductive material, thereby forming the conductive interconnect.
3. The method of claim 1 , further comprising:
fabricating a transistor having a gate and source/drain implant regions in the silicon substrate.
4. The method of claim 3 , further comprising:
forming an insulating material on the silicon substrate with the fabricated transistor; and
forming a contact coupled to the transistor.
5. The method of claim 4 , further comprising etching the via into the silicon substrate laterally adjacent to the transistor.
6. The method of claim 4 , further comprising extending the via deeper into the silicon substrate than the source/drain implant regions of the transistor.
7. The method of claim 4 , further comprising forming the contact generally parallel to the conductive interconnect.
8. The method of claim 1 , further comprising forming the first conductive path generally parallel to the second conductive path.
9. The method of claim 1 , further comprising forming the first conductive path generally parallel to the conductive interconnect.
10. The method of claim 1 , further comprising forming the second conductive path generally parallel to the conductive interconnect.
11. The method of claim 1 , further comprising forming the second metal routing structure generally perpendicular to the conductive interconnect.
12. The method of claim 1 , further comprising forming the second metal routing structure generally parallel to the first conductive path.
13. The method of claim 1 , further comprising forming the second metal routing structure generally parallel to the second conductive path.
14. The method of claim 1 , further comprising forming the first metal routing structure laterally spaced apart from the conductive interconnect.
15. The method of claim 1 , further comprising:
removing a portion of the second side of the silicon substrate to expose the second end of the conductive interconnect; and
forming a conductive redistribution structure proximate the second side of the silicon substrate and electrically coupled to the conductive interconnect.
16. The method of claim 15 , wherein the conductive redistribution structure comprises a conductive ball bond pad.
17. The method of claim 1 , wherein the conductive interconnect has a length to width ratio of about 5:1 to 10:1.
18. A method of fabricating a semiconductor device comprising:
etching a via into a silicon substrate from a first side toward a second side of the silicon substrate;
forming a conductive interconnect in the etched via, the conductive interconnect having a first end proximate the first side of the silicon substrate and a second end proximate the second side of the silicon substrate;
insulating the conductive interconnect with a first dielectric material proximate the first side of the silicon substrate;
forming a first metal routing structure on the first dielectric material, the first metal routing structure being at least partially in the first dielectric material;
insulating the conductive interconnect and the first metal routing structure with a second dielectric material;
forming a first opening generally corresponding to the first metal routing structure;
forming a second opening generally corresponding to the conductive interconnect;
filling the first opening with a conductive material to form a first conductive path;
filling the second opening with the conductive material to form a second conductive path generally parallel to the first conductive path;
electrically coupling the first conductive path and the second conductive path via a second metal routing structure.
19. The method of claim 18 , further comprising:
forming a third opening generally perpendicular to the first conductive path and the second conductive path;
filling the third opening with the conductive material to form the second metal routing structure.
20. The method of claim 18 , further comprising:
removing a portion of the second side of the silicon substrate to expose the second end of the conductive interconnect; and
forming a conductive redistribution structure proximate the second side of the silicon substrate;
electrically connecting the conductive redistribution structure with the conductive interconnect.
21. The method of claim 18 , wherein the conductive redistribution structure comprises a conductive ball bond pad.