IP Library Granted Patent US 10,217,524
Granted Patent B2
US 10,217,524 · App. 15/412,148 · Granted Feb 26, 2019

Autorecovery after manufacturing/system integration

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Quick Facts
Patent No.
US 10,217,524
App. No.
15/412,148
Granted
Feb 26, 2019
Kind
B2
Abstract

Methods of managing systems comprising a processor and a memory device external to the processor, including exposing the memory device to temperature levels associated with soldering, starting up the memory device and testing pre-programmed data using control circuitry of the memory device. When results of the testing indicate repair of the pre-programmed data should be performed, issuing a command from the processor to the memory device indicative of a desire for the memory device to repair the pre-programmed data, and in response to the memory device receiving the command, repairing the pre-programmed data using the control circuitry of the memory device.

Claims (35)

1. A method of managing a system comprising a processor and a memory device external to the processor, the method comprising:

exposing the memory device to heat of soldering the memory device to a platform of the system, then powering up the memory device;

testing pre-programmed data using control circuitry of the memory device, wherein the pre-programmed data comprises data programmed to the memory device prior to exposing the memory device to the heat of soldering the memory device to the platform;

in response to results of the testing indicating repair of the pre-programmed data should be performed, issuing a command from the processor to the memory device instructing the memory device to repair the pre-programmed data; and

in response to the memory device receiving the command, repairing the pre-programmed data using the control circuitry of the memory device.

2. The method of claim 1 , wherein powering up the memory device comprises powering up the memory device for a first time after exposing the memory device to the heat of soldering the memory device to the platform.

3. The method of claim 2 , wherein testing the pre-programmed data comprises testing the pre-programmed data in response to powering up the memory device.

4. The method of claim 1 , wherein testing the pre-programmed data comprises testing the pre-programmed data in response to a different command received by the memory device from the processor instructing the memory device to test the pre-programmed data.

5. The method of claim 1 , wherein testing the pre-programmed data comprises testing the pre-programmed data as part of an initialization process of the memory device.

6. The method of claim 1 , further comprising storing the results of the testing to registers of the memory device.

7. The method of claim 6 , further comprising the processor reading the results of the testing from the registers of the memory device to determine whether the results of the testing indicate that repair of the pre-programmed data should be performed.

8. The method of claim 1 , further comprising reporting the results of the testing to the processor for determining whether the results of the testing indicate repair of the pre-programmed data should be performed.

9. The method of claim 1 , wherein exposing the memory device to the heat of soldering the memory device to the platform comprises soldering the memory device to a platform configured to comprise the processor.

10. A method of managing a system comprising a processor and a memory device external to the processor, the method comprising:

exposing the memory device to heat of soldering the memory device to a platform of the system;

after exposing the memory device to the heat of soldering the memory device to the platform, powering up the memory device;

issuing a first command from the processor to the memory device instructing the memory device to test pre-programmed data of the memory device, wherein the pre-programmed data comprises data first programmed to the memory device prior to exposing the memory device to the heat of soldering the memory device to the platform;

in response to the memory device receiving the first command, testing the pre-programmed data using control circuitry of the memory device;

in response to results of the testing indicating repair of the pre-programmed data should be performed, issuing a second command from the processor to the memory device instructing the memory device to repair the pre-programmed data; and

in response to the memory device receiving the second command, repairing the pre-programmed data using the control circuitry of the memory device.

11. The method of claim 10 , further comprising storing the results of the testing to the memory device.

12. The method of claim 10 , further comprising either the processor reading the results of the testing from registers of the memory device to determine whether the results of the testing indicate that repair of the pre-programmed data should be performed, or the memory device reporting the results of the testing to the processor for determining whether the results of the testing indicate repair of the pre-programmed data should be performed.

13. The method of claim 10 , further comprising issuing the first command at a powering up of the memory device.

14. The method of claim 13 , further comprising re-issuing the first command at each subsequent powering up of the memory device.

15. The method of claim 10 , further comprising re-issuing the first command on a regular or intermittent schedule.

16. The method of claim 15 , wherein re-issuing the first command on the intermittent schedule comprises re-issuing the first command on a basis of increasing frequency over a life of the memory device.

17. A method of managing a system comprising a processor and a memory device external to the processor, the method comprising:

exposing the memory device to heat of soldering the memory device to a platform of the system;

powering up the memory device for a first time after exposing the memory device to the heat of soldering the memory device to the platform;

testing pre-programmed data of the memory device as part of an initialization process of the memory device, wherein the pre-programmed data comprises data first programmed to the memory device prior to exposing the memory device to the heat of soldering the memory device to the platform;

in response to results of the testing indicating, repair of the pre-programmed data should be performed, issuing a command from the processor to the memory device instructing the memory device to repair the pre-programmed data; and

in response to the memory device receiving the command, repairing the pre-programmed data using the control circuitry of the memory device.

18. The method of claim 17 , further comprising testing the pre-programmed data of the memory device as part of an initialization process of the memory device for a subsequent powering up of the memory device.

19. The method of claim 18 , further comprising testing the pre-programmed data of the memory device as part of an initialization process of the memory device for each subsequent powering up of the memory device.

20. The method of claim 17 , further comprising either the memory device storing the results of the testing to registers of the memory device and the processor reading the results of the testing from the registers of the memory device to determine whether the results of the testing indicate that repair of the pre-programmed data should be performed, or the memory device reporting the results of the testing to the processor for determining whether the results of the testing indicate repair of the pre-programmed data should be performed.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →