IP Library Granted Patent US 9,888,574
Granted Patent B1
US 9,888,574 · App. 15/399,664 · Granted Feb 6, 2018

Apparatus and methods for via connection with reduced via currents

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Quick Facts
Patent No.
US 9,888,574
App. No.
15/399,664
Granted
Feb 6, 2018
Kind
B1
Abstract

Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

Claims (71)

1. An apparatus comprising:

a printed circuit board (PCB); and

an electronic component mounted on the PCB, the electronic component comprising at least one pin,

wherein the PCB comprises:

a multi-level plane structure comprising first, second and third planes, wherein the first plane includes a first conductive region, the second plane includes a second conductive region, and the third plane includes a third conductive region,

wherein the first, second and third planes are disposed at different levels from one another,

wherein the first conductive region includes a first portion projecting from a part of the first conductive region, a second portion and a third portion between the first and second portions, wherein the second conductive region includes fourth and fifth portions corresponding respectively to the second and third portions of the first conductive region, and wherein the third conductive region includes a sixth portion corresponding to the fourth portion of the second conductive region;

a first conductive via forming a first electrical path between the third portion of the first conductive region and the fifth portion of the second conductive region without an intervention of the third conductive region;

a second conductive via forming a second electrical path between the second portion of the first conductive region and one of the fourth portion of the second conductive region and the sixth portion of the third conductive region; and

a third conductive via forming a third electrical path between the fourth portion of the second conductive region and the sixth portion of the third conductive region, and

wherein the at least one pin of the electronic component is coupled to the first portion of the first conductive region.

2. The apparatus of claim 1 , wherein the third conductive region is placed between the first and second conductive regions, and wherein the second conductive via forms the second electrical path between the second portion of the first conductive region and the sixth portion of the third conductive region.

3. The apparatus of claim 2 ,

wherein the first conductive region further includes a seventh portion opposite to the third portion with respect to the second portion,

wherein the second conductive region further includes an eighth portion opposite to the fifth portion with respect to the fourth portion,

wherein the third conductive region further includes a ninth portion corresponding to the seventh and eighth portions,

wherein the PCB further comprises:

a fifth conductive via forming a fourth electrical path between the eighth and ninth portions, and

wherein the seventh and ninth portions are electrically insulated.

4. The apparatus of claim 1 , wherein the second conductive region is placed between the first and third conductive regions, and

wherein the second conductive via forms the second electrical path between the second portion of the first conductive region and the fourth portion of the second conductive region.

5. The apparatus of claim 1 , wherein an impedance of the first electrical path is greater than an impedance of the second electrical path.

6. An apparatus comprising:

a first layer including a first conductive plate;

a component on the first layer;

a second layer including a second conductive plate, wherein the second conductive plate is configured to be coupled to an external power source;

a third layer between the first layer and the second layer, wherein the third layer includes a third conductive plate;

a first via configured to couple the first conductive plate to the second conductive plate and the third conductive plate; and

a second via coupled the first conductive plate,

wherein the first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component, and

wherein the second via is further coupled to either the second conductive plate or the third conductive plate while being decoupled from the third conductive plate or the second conductive plate respectively.

7. The apparatus of claim 6 , wherein the second via is coupled to the second conductive plate and insulated from the third conductive plate.

8. The apparatus of claim 7 , wherein the second via is coupled to the third conductive plate and insulated from the second conductive plate.

9. The apparatus of claim 8 , further comprising a third via coupled to the second conductive plate and the third conductive plate.

10. The apparatus of claim 9 , wherein the third via is insulated from the first conductive plate.

11. The apparatus of claim 9 , wherein the third via is located opposite to the second via with respect to the first via.

12. The apparatus of claim 6 , wherein the second via is coupled to the third conductive plate and insulated from the second conductive plate.

13. The apparatus of claim 12 , wherein the second via is shorter than a distance between the first conductive plate and the second conductive plate.

14. The apparatus of claim 12 , wherein the first via is further coupled to the third conductive plate.

15. The apparatus of claim 12 , further comprising a third via insulated from the first conductive plate,

wherein the second via is coupled to the third via on a third conductive plate on the third layer.

16. The apparatus of claim 15 , wherein the third via is located opposite to the second via with respect to the first via.

17. The apparatus of claim 15 , wherein the third via is further coupled to the second conductive plate.

18. The method of claim 15 , wherein the third via is insulated from the second conductive plate.

19. An apparatus comprising:

a first layer including a first conductive plate;

a component on the first layer;

a second layer including a second conductive plate;

a third layer including a third conductive plate;

a first via configured to couple the first conductive plate to the second conductive plate, wherein the first via is coupled to the first conductive plate at a first node, and wherein the first via is further coupled to the third conductive plate;

a first electrical path coupling the component to the second conductive plate, wherein the first electrical path includes the first via;

a second via configured to couple the first conductive plate to the second conductive plate, wherein the second via is coupled to the first conductive plate at a second node; and

a second electrical path coupling the component to the second conductive plate, wherein the second electrical path includes the second via,

wherein an impedance between the first node and the component is greater than an impedance between the second node and the component, and

wherein an impedance of the second electrical path impedance is greater than an impedance of the first electrical path.

20. The apparatus of claim 19 ,

wherein the third layer is between the first layer and the second layer.

21. The apparatus of claim 19 ,

wherein the second layer is between the first layer and the third layer.

22. An apparatus comprising:

a first layer including a first conductive plate;

a component on the first layer to be coupled to the first conductive plate wherein the component is placed in proximity to a first portion of the first conductive plate and away from a second portion of the first conductive plate;

a second layer including a third portion and a second conductive plate, wherein the second conductive plate comprises a fourth portion corresponding to the first and second portions respectively and wherein the third portion is insulated from the second conductive plate;

a third layer between the first layer and the second layer, wherein the third layer includes a third conductive plate comprising a fifth portion and a sixth portion corresponding to the first and second portions respectively;

a first via configured to couple the second portion of the first conductive plate to the sixth portion of the third conductive plate and the fourth portion of the second conductive plate; and

a second via configured to couple the first portion of the first conductive plate to the fifth portion of the third conductive plate wherein the second via is isolated from the second conductive plate.

23. The apparatus of claim 22 , further comprising:

a third via configured to couple a seventh portion of the first conductive plate to an eight portion of the third conductive plate and a ninth portion of the second conductive plate, wherein the second portion is between the seventh portion and the component;

a fourth layer comprising a fourth conductive plate, wherein the second layer is between the fourth layer and the third layer, and

a fourth via configured to couple a tenth portion of the second conductive plate to the fourth conductive plate, wherein the tenth portion is between the fourth and eighth portions of the second layer.

24. The apparatus of claim 23 , wherein a diameter of the fourth via is greater than a diameter of at least one of the first to third via.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2017
From: MORISHIMA, ATSUSHI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040866/0761 →