Arrays of memory cells and methods of forming an array of memory cells
View Patent ↗An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.
1. An array of memory cells, comprising:
buried access lines comprising conductively doped semiconductor material;
pillars extending elevationally outward of and spaced along the buried access lines, the pillars individually comprising a memory cell;
outer access lines elevationally outward of the pillars and the buried access lines, the outer access lines being of higher electrical conductivity than the buried access lines;
a plurality of conductive vias spaced along and electrically coupling pairs of individual of the buried and outer access lines, a plurality of the pillars being between immediately adjacent of the vias along the pairs; and
electrically conductive metal material directly against tops of the buried access lines and extending between the pillars along the individual buried access lines, the conductive metal material having a concave arcuate elevationally outer surface that is between immediately adjacent of the conductive pillars between the immediately adjacent vias.
2. The array of claim 1 wherein the individual pillars comprise a select device between its buried access line and its memory cell.
3. The array of claim 1 wherein the memory cells individually comprise a pair of electrodes having phase change material there-between.
4. The array of claim 3 wherein the memory cells individually comprise heater material between the pair of electrodes, the heater material comprising an angled plate structure having a first portion and a second portion that extends elevationally outward from the first portion.
5. The array of claim 3 wherein the pair of electrodes comprises elevationally outer and inner electrodes, the elevationally outer electrode comprising a sense line that electrically couples pillars extending from different individual buried access lines.
6. The array of claim 5 wherein the phase change material is in individual lines that are elevationally inward of and extend along individual of the select lines.
7. The array of claim 1 where electrical contact resistance between the metal material and the conductively doped semiconductor material is less than half of intrinsic electrical resistance of the conductively doped semiconductor material.
8. The array of claim 1 wherein that portion of the metal material that is directly against the buried access line tops is a metal silicide.
9. The array of claim 8 wherein that portion of the conductively doped buried access lines which the metal silicide is directly against comprises elemental silicon.
10. The array of claim 8 wherein the metal material consists essentially of the metal silicide.
11. The array of claim 8 wherein the metal material is not homogenous and comprises metal other than the metal silicide that is directly against the metal silicide.
12. The array of claim 1 wherein that portion of the metal material that is directly against the buried access line tops is not a metal silicide.
13. The array of claim 12 wherein said portion is at least one of a metal compound consisting of elements other than that of the conductively doped semiconductor material, an elemental metal, and an alloy of elemental metals.
14. The array of claim 12 wherein the metal material is devoid of metal silicide.
15. The array of claim 1 wherein the metal material extends to elevationally under the pillars.
16. The array of claim 15 wherein the metal material interconnects with itself under the pillars.
17. The array of claim 15 wherein the metal material does not interconnect with itself under the pillars.
18. The array of claim 1 wherein the metal material does not extend to under the pillars.
19. An array of memory cells, comprising:
buried access lines comprising conductively doped semiconductor material;
pillars extending elevationally outward of and spaced along the buried access lines, the pillars individually comprising a memory cell;
outer access lines elevationally outward of the pillars and the buried access lines, the outer access lines being of higher electrical conductivity than the buried access lines;
a plurality of conductive vias spaced along and electrically coupling pairs of individual of the buried and outer access lines, a plurality of the pillars being between immediately adjacent of the vias along the pairs; and
electrically conductive metal material directly against tops of the buried access lines and extending between the pillars along the individual buried access lines, that portion of the metal material that is directly against the buried access line tops being a metal silicide, the metal silicide extending to elevationally under the pillars, the metal silicide having a concave arcuate elevationally outer surface that is between immediately adjacent of the conductive pillars between the immediately adjacent vias.
20. The array of claim 1 comprising a dielectric liner against sidewalls of the pillars, the conductive metal material being directly under the dielectric liner, the concave arcuate elevationally outer surface not being directly beneath the dielectric liner.
21. The array of claim 1 wherein the conductive material has a planar elevationally outermost surface that is between the immediately adjacent conductive pillars between the immediately adjacent vias.
22. The array of claim 1 wherein the conductive material has two spaced planar elevationally outermost surfaces that are between the immediately adjacent conductive pillars between the immediately adjacent vias.
23. The array of claim 1 wherein the conductive material has two spaced planar elevationally outermost surfaces that individually join with and at opposite ends of the concave arcuate elevationally outer surface between the immediately adjacent conductive pillars between the immediately adjacent vias.
24. The array of claim 1 wherein the conductive metal material has a convex arcuate elevationally inner surface between the immediately adjacent conductive pillars between the immediately adjacent vias.
25. An array of memory cells, comprising:
buried access lines comprising conductively doped semiconductor material;
pillars extending elevationally outward of and spaced along the buried access lines, the pillars individually comprising a memory cell;
outer access lines elevationally outward of the pillars and the buried access lines, the outer access lines being of higher electrical conductivity than the buried access lines;
a plurality of conductive vias spaced along and electrically coupling pairs of individual of the buried and outer access lines, a plurality of the pillars being between immediately adjacent of the vias along the pairs; and
electrically conductive metal material directly against tops of the buried access lines and extending between the pillars along the individual buried access lines, the conductive metal material having a convex arcuate elevationally inner surface that is between immediately adjacent of the conductive pillars between the immediately adjacent vias.