Methods and apparatuses having strings of memory cells and select gates with double gates
An apparatus, a method, and a system are disclosed. The apparatus includes a string of memory cells coupled to a select gate drain transistor that has a front control gate and a back control gate. The front and back control gates can be coupled together such that they are biased at the same voltage or separate such that they can be biased at different voltages.
1. A method comprising:
biasing a control gate of a selected memory cell with a first voltage;
biasing control gates of a first group of multiple unselected memory cells with a second voltage;
biasing a first control gate of a dual gate select drain transistor with a first enable voltage; and
biasing a second control gate of the dual gate select drain transistor with a second enable voltage, wherein the first control gate of the dual gate select drain transistor extends around at least a portion of the second control gate of the dual gate select drain transistor.
2. The method of claim 1 wherein the first voltage is a read voltage and the second voltage is a read pass voltage.
3. The method of claim 1 wherein the first voltage is a program voltage and the second voltage is a program pass voltage.
4. The method of claim 1 wherein the first enable voltage and the second enable voltage are the same voltage.
5. The method of claim 1 wherein the selected memory cell and the multiple unselected memory cells, are coupled together in a first string of memory cells of a memory device, the first string coupled to the dual gate select drain transistor; the memory device further comprising a second string of memory cells including a second group of multiple memory cells, the second string coupled to a second dual gate select drain transistor, the method further comprising:
biasing a first control gate of the second dual gate select drain transistor with a first disable voltage; and
biasing a second control gate of the unselected second dual gate select drain transistor with a second disable voltage.
6. The method of claim 5 wherein the first disable voltage is greater than the second disable voltage.
7. The method of claim 5 , wherein one of the first and second disable voltages comprises a negative voltage.
8. The method of claim 7 wherein the first or the second disable voltage that is not negative is a reference voltage.
9. A method of operating a memory, comprising:
biasing a control gate of a selected memory cell in a first memory cell string with a first voltage, the first memory cell string including a first group of memory cells;
biasing control gates of unselected memory cells in the first memory cell string with a second voltage;
biasing a first control gate of a first dual gate select drain transistor in the first memory cell string with a third voltage; and
biasing a second control gate of the first dual gate select drain transistor in the first memory cell string with a fourth voltage, wherein the first control gate of the first dual gate select drain transistor extends around at least a portion of the second control gate of the first dual gate select drain transistor;
biasing a first control gate of a second dual gate select drain transistor in a second memory cell string with a fifth voltage, the second memory cell string including a second group of memory cells; and
biasing a second control gate of the second dual gate select drain transistor in the second memory cell string with a sixth voltage, wherein the first control gate of the second dual gate select drain transistor extends around at least a portion of the second control gate of the second dual gate select drain transistor.
10. The method of claim 9 , wherein the third voltage is a first enable voltage, and wherein the fourth voltage is a second enable voltage.
11. The method of claim 10 , wherein the fifth voltage is a first disable voltage, and wherein the sixth voltage is a second disable voltage.
12. The method of claim 9 , wherein the first and second memory cell strings each comprise a respective pillar, and wherein in each of the first and second memory cell strings the first control gate of the respective dual gate select drain transistor surrounds a portion of the pillar, and the second control gate of the respective dual gate select drain transistor comprises a portion extending over the pillar, and an extension extending into the pillar.
13. The method of claim 9 , wherein the third voltage applied to the first control gate of the first dual gate select drain transistor and the fourth voltage applied to the second control gate of the first dual gate select drain transistor are the same voltage.
14. The method of claim 9 , wherein the third voltage applied to the first control gate of the first dual gate select drain transistor and the fourth voltage applied to the second control gate of the first dual gate select drain transistor are different from one another.
15. The method of claim 9 , wherein the third voltage applied to the first control gate of the first dual gate select drain transistor and the fourth voltage applied to the second control gate of the first dual gate select drain transistor are different from one another during at least one of a program or read operation.
16. The method of claim 9 , wherein the third voltage applied to the first control gate of the first dual gate select drain transistor and the fourth voltage applied to the second control gate of the first dual gate select drain transistor are the same voltage during an erase operation.