Program and read trim setting
A trim set register for a memory device has a plurality of individual trim settings. Each trim setting has a program trim value, a step-up trim value, and a program pulse width. A trim setting may be assigned to a portion of the memory device based on a program speed of the portion of the memory device.
1. A trim set register for a memory device, the register comprising:
a plurality of individual trim settings, each trim setting of the plurality of individual trim settings comprising a program trim value, a step-up trim value, and a program pulse width;
wherein a first trim setting of the plurality of individual trim settings is assigned to a first portion of a particular row of memory cells of the memory device;
wherein a second trim setting of the plurality of individual trim settings is assigned to a second portion of the particular row of memory cells; and
wherein a third trim setting of the plurality of individual trim settings is assigned to a first portion of a different row of memory cells of the memory device.
2. The trim set register of claim 1 , wherein the plurality of individual trim settings comprises four.
3. The trim set register of claim 1 , wherein the plurality of individual trim settings comprises three.
4. The trim set register of claim 1 , wherein the plurality of individual trim settings is 2 n , where n is a positive integer.
5. The trim set register of claim 1 , wherein the plurality of individual trim settings are in a trim set register having a register entry for each of the plurality of individual trim settings.
6. The trim set register of claim 1 , wherein the second trim setting of the plurality of individual trim settings is assigned to a second portion of the different row of memory cells.
7. The trim set register of claim 1 , wherein a fourth trim setting of the plurality of individual trim settings is assigned to a second portion of the different row of memory cells.
8. A trim set register for a memory device, the register comprising:
a plurality of individual trim settings, each trim setting of the plurality of individual trim settings comprising a program trim value, a step-up trim value, and a program pulse width;
wherein the plurality of individual trim settings include trim set parameters for:
a wide active area and a wide gate;
a wide active area and a narrow gate;
a narrow active area and a wide gate; and
a narrow active area and a narrow gate.
9. The trim set register of claim 8 , wherein the trim set parameters for the wide active area and the narrow gate and for the narrow active area and the wide gate are the same.
10. A trim set register for a memory device, the register comprising:
a plurality of individual trim settings, each trim setting of the plurality of individual trim settings comprising a program trim value, a step-up trim value, and a program pulse width;
wherein the plurality of individual trim settings include trim set parameters for fast programming portions, first intermediate speed programming portions, second intermediate speed programming portions, and slow programming portions.
11. The trim set register of claim 10 , wherein the trim set parameters for the first intermediate speed programming portions and the second intermediate speed programming portions are the same.
12. A trim set register for a memory device, the register comprising:
a plurality of individual trim settings, each trim setting of the plurality of individual trim settings comprising a program trim value, a step-up trim value, and a program pulse width;
wherein the plurality of individual trim settings includes trim set parameters for:
an even row and an even column;
an even row and an odd column;
an odd row and an even column; and
an odd row and odd column.
13. The trim set register of claim 12 , wherein the trim set parameters for the even row and the even column and for the odd row and the even column are the same.
14. A trim set register for a memory device, the register comprising:
a plurality of individual trim settings, each trim setting of the plurality of individual trim settings comprising a program trim value, a step-up trim value, and a program pulse width;
wherein a trim setting from one of the plurality of individual trim settings is assigned to a portion of the memory device based on a program speed of the portion of the memory device.
15. The trim set register of claim 14 , wherein the portion of the memory device comprises an edge block of memory cells.
16. The trim set register of claim 14 , wherein the portion of the memory device comprises a center block of memory cells.
17. The trim set register of claim 14 , wherein program speed of the portion of the memory device is determined from testing the portion of the memory device.
18. A trim set register for a memory device, the register comprising:
a plurality of individual trim settings, each trim setting comprising a program trim value, a step-up trim value, and a program pulse width;
wherein a best one of the plurality of individual trim settings is assigned to each portion of a plurality of portions of the memory device based on a determined programming speed for each of the plurality of portions of the memory device.
19. The trim set register of claim 18 , wherein the plurality of portions of the memory device are a plurality of pages of the memory device, wherein the best one of the plurality of trim settings being assigned to each portion of the plurality of portions of the memory device comprises the best one of the plurality of trim settings being assigned to each page of the plurality of pages of the memory device.
20. The trim set register of claim 18 , wherein the plurality of portions of the memory device are a plurality of blocks of the memory device, wherein the best one of the plurality of trim settings being assigned to each portion of the plurality of portions of the memory device comprises the best one of the plurality of trim settings being assigned to each block of the plurality of blocks of the memory device.
21. The trim set register of claim 18 , wherein the plurality of portions of the memory device are a plurality of columns of the memory device, wherein the best one of the plurality of trim settings being assigned to each portion of the plurality of portions of the memory device comprises the best one of the plurality of trim settings being assigned to each column of the plurality of columns of the memory device.
22. A trim set register for a memory device, the register comprising:
a plurality of individual trim settings, each trim setting comprising a program trim value, a step-up trim value, and a program pulse width;
wherein a best one of the plurality of individual trim settings is assigned for each respective column of memory cells of the memory device of a plurality of columns of memory cells of the memory device.
23. The trim set register of claim 22 , wherein the plurality of individual trim settings are tested to determine which trim setting of the plurality of individual trim settings is best for the respective column of memory cells of the memory device.