Floating body transistors and memory arrays comprising floating body transistors

1. A floating body transistor, comprising:

a gate structure configured as a bracket having two upwardly-projecting sidewalls joined to a base; a region between the upwardly-projecting sidewalls and over the base being an interior region of the bracket; the interior region of the bracket having an interior surface along an upper surface of the base, and along inward surfaces of the upwardly-projecting sidewalls; the sidewalls being a first sidewall and a second sidewall; the first sidewall having a first notch extending downwardly therein, and the second sidewall having a second notch extending downwardly therein; the first and second notches being horizontally aligned with one another;

dielectric material lining the interior surface of the bracket;

a semiconductor material body within the interior region of the bracket and spaced from the bracket by the dielectric material; and

the semiconductor material body having a third notch extending therein, with said third notch being horizontally aligned with the first and second notches.

2. The floating body transistor of claim 1 wherein the semiconductor material body has a lower trunk region and bifurcates into two branches projecting upwardly from the lower trunk region and extending along the third notch; the branches being a first branch on one side of the third notch and a second branch on the other side of the third notch; the branches comprising heavily-doped source/drain regions, and a channel region extending between the heavily-doped source/drain regions and under the third notch.

3. The floating body transistor of claim 1 wherein the semiconductor material body comprises silicon, and wherein the dielectric material comprises silicon dioxide.

4. The floating body transistor of claim 1 wherein the gate structure comprises conductively-doped silicon.

5. The floating body transistor of claim 1 wherein the gate structure comprises metal.

6. A memory array, comprising:

a wordline;

a plurality of floating body transistors along the wordline; each of the floating body transistors comprising:

a gate structure configured as a bracket having two upwardly-projecting sidewalls joined to a base; a region between the upwardly-projecting sidewalls and over the base being an interior region of the bracket; the interior region of the bracket having an interior surface along an upper surface of the base, and along inward surfaces of the upwardly-projecting sidewalls; the sidewalls being a first sidewall and a second sidewall; the first sidewall having a first notch extending downwardly therein, and the second sidewall having a second notch extending downwardly therein; the first and second notches being horizontally aligned with one another;

dielectric material lining the interior surface of the bracket;

a semiconductor material body within the interior region of the bracket and spaced from the bracket by the dielectric material; and

the semiconductor material body having a third notch extending therein, with said third notch being horizontally aligned with the first and second notches; wherein the semiconductor material body has a lower trunk region electrically coupled with the wordline, and bifurcates into two branches projecting upwardly from the lower trunk region and extending along the third notch; the branches being a first branch on one side of the third notch and a second branch on the other side of the third notch; the first branch comprising a first source/drain region and the second branch comprising a second source/drain region;

digit lines electrically coupled with the first source/drain regions; and

charge-storage devices electrically coupled with the second source/drain regions.

7. The memory array of claim 6 wherein each of the semiconductor material bodies has a channel region between the first and second source/drain regions and extending to under the third notch.

8. The memory array of claim 6 wherein the charge-storage devices are capacitors.

9. The memory array of claim 6 wherein the charge-storage devices are ferroelectric capacitors.

10. The memory array of claim 6 wherein the semiconductor material bodies comprise silicon, and wherein the dielectric material comprises silicon dioxide.

11. The memory array of claim 6 wherein the gate structures comprise conductively-doped silicon.

12. The memory array of claim 6 wherein the gate structures comprise metal.

13. The memory array of claim 6 wherein an upper surface of the wordline comprises metal, and wherein the gate structures comprise conductively-doped silicon which is directly against the metal of the upper surface of the wordline.

14. A memory array, comprising:

a plurality of spaced-apart capacitors;

a plurality of floating body transistors over the capacitors and in one-to-one correspondence with the capacitors; each of the floating body transistors comprising:

a gate structure configured as a bracket having two upwardly-projecting sidewalls joined to a base; a region between the upwardly-projecting sidewalls and over the base being an interior region of the bracket; the interior region of the bracket having an interior surface along an upper surface of the base, and along inward surfaces of the upwardly-projecting sidewalls; the sidewalls being a first sidewall and a second sidewall; the first sidewall having a first notch extending downwardly therein, and the second sidewall having a second notch extending downwardly therein; the first and second notches being horizontally aligned with one another;

dielectric material lining the interior surface of the bracket;

a semiconductor material body within the interior region of the bracket and spaced from the bracket by the dielectric material; and

the semiconductor material body having a third notch extending therein, with said third notch being horizontally aligned with the first and second notches; wherein the semiconductor material body has a lower trunk region electrically coupled with one of the capacitors, and bifurcates into two branches projecting upwardly from the lower trunk region and extending along the third notch; the branches being a first branch on one side of the third notch and a second branch on the other side of the third notch; the first branch comprising a first source/drain region and the second branch comprising a second source/drain region;

first conductive lines electrically coupled with the first source/drain regions; and

second conductive lines electrically coupled with the second source/drain regions.

15. The memory array of claim 14 wherein the capacitors are ferroelectric capacitors.

16. The memory array of claim 14 wherein the semiconductor material bodies comprise silicon, and wherein the dielectric material comprises silicon dioxide.

17. The memory array of claim 14 wherein the gate structures comprise conductively-doped silicon.

18. The memory array of claim 14 wherein the gate structures comprise metal.

19. The memory array of claim 14 wherein upper surfaces of the capacitors comprises metal, and wherein the gate structures comprise conductively-doped silicon which is directly against the metal of the upper surfaces of the capacitors.

20. The memory array of claim 14 wherein the first conductive lines are at power supply voltage, Vcc; and the second conductive lines are at a ground voltage, Vss.