Wiring with external terminal

1. An apparatus comprising a semiconductor chip, wherein the semiconductor chip comprises:

an edge defining a termination of the semiconductor chip;

a pad formation area along the edge, the pad formation area including a plurality of pads arranged along the edge;

a circuit block comprising a transistor, a via coupled to the transistor, and a first circuit associated with the transistor; and

a distribution conductor coupling the via to a corresponding one of the plurality of pads,

wherein the first circuit is displaced between the pad formation area and the via.

2. The apparatus of claim 1 , wherein the transistor is arranged between the first circuit and the via.

3. The apparatus of claim 1 ,

wherein the circuit block further comprises a second circuit associated with the first circuit; and

wherein the second circuit is formed in the pad formation area under at least one of the plurality of pads.

4. The apparatus of claim 3 , wherein the at least one of the plurality of pads is different from the corresponding one of the plurality of pads, and the corresponding one of the plurality of pads is located far from the circuit block.

5. The apparatus of claim 1 ,

wherein the semiconductor chip further comprises a multi-level wiring structure,

wherein the multi-level wiring structure comprises at least a first-level wiring layer and a second-level wiring layer, the first-level wiring layer including one or more first conductors and a first interlayer insulating film covering the one or more first conductors, and the second-level wiring layer including one or more second conductors and a second interlayer insulating film covering the one or more second conductors, and

wherein the distribution conductive layer is greater in thickness than each of the one or more first and second conductors.

6. The apparatus of claim 5 , wherein the distribution conductive layer is at least five times as thick as each of the one or more first and second conductors.

7. The apparatus of claim 5 , wherein the distribution conductive layer is more than five times as thick as each of the one or more first and second conductors.

8. The apparatus of claim 1 , wherein the pad and the conductor are made of a distribution conductive layer.

9. The apparatus of claim 8 , wherein the distribution conductive layer is made of a middle conductivity material.

10. A semiconductor chip, comprising:

a pad included in a pad formation area, the pad configured to be coupled to external circuitry;

a first circuit comprising a via coupled to the pad;

a distribution conductive layer comprising the pad and a conductor that couples the pad and the via;

a first wiring layer comprising a first metal layer; and

a second wiring layer between the first wiring layer and the distribution conductive layer, comprising a second metal layer,

wherein the via is disposed along a first side of the first circuit that is opposite to a second side of the first circuit, wherein the pad formation area extends along the second side of the first circuit, and

wherein the via is made of the second metal layer.

11. The semiconductor chip of claim 10 , wherein the second metal layer is made of a middle conductivity material.

12. The semiconductor chip of claim 10 , wherein at least a portion of the first circuit is disposed on the first wiring layer.

13. The semiconductor chip of claim 12 , further comprising a semiconductor substrate that is at an opposite side to the second wiring layer with respect to the first wiring layer,

wherein the first circuit comprises at least one transistor made, at least in part, of the semiconductor substrate.

14. The semiconductor chip of claim 10 , wherein the first metal layer is made of a low conductivity material; and

wherein the first circuit comprises at least one resistor made of the first metal layer.

15. The semiconductor chip of claim 11 , wherein the first circuit comprises:

a read path comprising a first conversion circuit, configured to receive first read data from the memory cell array, to convert the first read data in parallel into second read data in serial and further configured to provide the second read data to the via;

a write path comprising a second conversion circuit, configured to receive first write data in serial from the via; to convert the first write data into second write data in parallel and further configured to provide the second write data to the memory cell array.

16. An apparatus comprising:

a pad formation area including a plurality of pads disposed at an edge of the apparatus;

a peripheral circuit area including a plurality of circuit blocks coupled to a memory cell array, each circuit block of the plurality of circuit blocks comprising a via disposed at a side opposite to the pad formation area with respect to each circuit block; and

a plurality of conductors, each conductor coupling the via to the corresponding pad, and crossing over, at least in part, an area in the peripheral circuit area that is outside the circuit block comprising the via.

17. The apparatus of claim 16 , wherein each conductor coupling the via to the corresponding pad crosses over an adjacent circuit block of the circuit block comprising the via.

18. The apparatus of claim 16 , wherein a total width of the plurality of circuit blocks along the edge is larger than a total width of the plurality of pads along the edge.

19. The apparatus of claim 16 , further comprising a clock line coupled to each circuit block of the circuit blocks and configured to provide a clock signal.