Apparatus and method for a PVT independent RC delay

1. A delay circuit configured to receive an input signal and to provide a delayed representation of the input signal at an output, the delay circuit comprising:

an input inverter having an input configured to directly receive the input signal of the delay circuit;

a resistor configured to pass a compensation current;

a capacitor configured to receive a charge current based on the compensation current;

a first compensation circuit configured to provide a control signal, the first compensation circuit comprising:

an inverter circuit configured to track an inverter threshold voltage across process, voltage and temperature variations, wherein an output of the inverter circuit is directly coupled to an input of the inverter circuit;

an amplifier configured to receive the output of the inverter circuit an provide the control signal at an amplifier output;

a charge-current coupling circuit configured to receive the control signal and to provide the compensation current and the charge current; and

a second compensation circuit configured to modulate a portion of the compensation current to alleviate temperature variation effects cause by the resistor, the second compensation circuit having a first node of a mirror transistor of a current mirror coupled to a first node of the resistor and a second node of the mirror transistor coupled to a second node of the resistor, a sense transistor of the current mirror configured to receive a sense current that is proportional to absolute temperature and to modulate a portion of the compensation current using the mirror transistor of the current mirror.

2. The delay circuit of claim 1 , wherein the charge-current coupling circuit includes a first control transistor, having a control node coupled directly to the amplifier output, configured to provide the compensation current.

3. The delay circuit of claim 2 , wherein the charge-current coupling circuit includes a second control transistor, having a control node coupled directly to the amplifier output, configured to provide the charge current.

4. The delay circuit of claim 3 , including an interface circuit configured to receive the input signal and to provide the delayed representation of the input signal, the interface circuit including the input inverter and a delay enable transistor coupled in series with the second control transistor of the charge-current coupling circuit; and

wherein an output of the input inverter is coupled to a control node of the delay enable transistor.

5. The delay circuit of claim 3 , wherein the charge-current coupling circuit includes a matching transistor coupled in series with the first control transistor.

6. The delay circuit of claim 4 , wherein the interface circuit includes an output circuit configured to receive a charge voltage of the capacitor and to provide the delayed representation of the input signal, wherein the delayed representation of the input signal includes a delayed representation of a transition of the input signal, and wherein the charge current is indicative, in part, of the process, voltage and temperature variation of a trip voltage of the output circuit.

7. The delay circuit of claim 6 , wherein the output circuit includes one or more output inverters and wherein the charge current is indicative, in part, of the process, voltage and temperature variation of a trip voltage of the one or more output inverters.

8. The delay circuit of claim 6 , including a second circuit configured to receive the control signal and to provide a second delayed representation of the input signal at a second output, the second circuit comprising:

a second capacitor configured to receive a second charging current; and

a second charge-current coupling circuit configured to receive the control signal and to provide the second charge current.

9. A method for providing a delayed representation of an input signal at an output of a delay circuit, the method comprising:

receiving the input signal of the delay circuit directly at an input inverter;

passing a compensation current at a resistor of the delay circuit;

generating a charge current representative of the compensation current;

receiving the charge current at a capacitor of the delay circuit;

tracking an inverter threshold voltage of an inverter circuit of a first compensation circuit across process, voltage and temperature variations using an output of the inverter circuit, wherein the output of the inverter circuit is directly coupled to an input of the inverter circuit,

receiving the output of the inverter circuit at an amplifier of the first compensation circuit;

providing a control signal at an output of the amplifier;

receiving the control signal at a charge-current coupling circuit;

providing the compensation current and the charge current using the charge-current coupling circuit and the control signal;

modulating a portion of the compensation current to alleviate temperature variation effects of the resistor using a second compensation circuit, wherein the modulating includes receiving a sense current that is proportional to absolute temperature at a sense transistor of a current mirror of the second compensation circuit, and modulating the portion of the compensation current using a mirror transistor, of the current mirror, coupled across the resistor.

10. The method of claim 9 , including:

receiving the control signal at a control node of a first control transistor of the charge-current coupling circuit; and

providing the compensation current using the first control transistor.

11. The method of claim 10 , including:

receiving the control signal at a control node of a second control transistor of the charge-current coupling circuit; and

providing the charge current using the second control transistor.

12. The method of claim 11 , including:

receiving the input signal at an interface circuit of the delay circuit, the interface circuit including the input inverter;

providing the delayed representation of the input signal at an output of the interface circuit,

controlling the charge current to the capacitor using a delay enable transistor of the interface circuit, the delay enable transistor coupled in series with the second control transistor of the charge-current coupling circuit.

13. The method of claim 12 , including maintaining a matching transistor in a low impedance state, the matching transistor coupled in series with the first control transistor.

14. The method of claim 13 , including:

providing a charge control signal in a delay enable state to the delay enable transistor when the input signal is in a first state, the delay enable state configured to enable the delay enable transistor to couple the charge current with the capacitor.

15. The method of claim 13 , includes:

receiving a charge voltage of the capacitor at an output circuit of the interface circuit;

providing the delayed representation of the input signal at an output of the output circuit,

wherein the delayed representation of the input signal includes a delayed representation of a transition of the input signal, and

wherein the charge current is indicative, in part, of the process, voltage and temperature variation of a trip voltage of the output circuit.

16. The method of claim 15 , wherein the output circuit includes one or more output inverters; and

wherein the charge current is indicative, in part, of the process, voltage and temperature variation of a trip voltage of the one or more output inverters.