IP Library Granted Patent US 10,403,575
Granted Patent B2
US 10,403,575 · App. 15/405,711 · Granted Sep 3, 2019

Interconnect structure with nitrided barrier

Inventors: Gregory C. Herdt (Boise, ID); Mikhail A. Treger (Boise, ID); Jin Lu (Boise, ID)
Assignee: Micron Technology, Inc.
H01L23/53238H01L21/76847H01L21/76898H01L23/481
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Quick Facts
Patent No.
US 10,403,575
App. No.
15/405,711
Granted
Sep 3, 2019
Kind
B2
Abstract

Semiconductor device interconnect structures comprising nitrided barriers are disclosed herein. In one embodiment, an interconnect structure includes a conductive material at least partially filling an opening in a semiconductor substrate, and a nitrided barrier between the conductive material and a sidewall in the opening. The nitrided barrier comprises a nitride material and a barrier material, such as tantalum, between the nitride material and the sidewall of the substrate.

Claims (41)

1. A method of manufacturing a semiconductor device, the method comprising:

forming an opening in a semiconductor substrate, wherein the semiconductor substrate includes a sidewall in the opening; and

forming an interconnect structure at least within the opening, wherein forming the interconnect structure includes:

depositing under vacuum a first barrier material over the sidewall of the semiconductor substrate, wherein the first barrier material comprises titanium,

depositing under vacuum a second barrier material over the first barrier material, wherein the second barrier material comprises tantalum,

forming a nitride material from the second barrier material, wherein forming the nitride material includes flowing a process gas comprising reactive nitrogen over a surface of the second barrier material without breaking the vacuum, and wherein the second barrier material is deposited over the first barrier material before flowing the process gas, and

depositing a conductive material within a volume defined by the nitride material.

2. The method of claim 1 wherein forming the interconnect structure further includes forming an intermediary material between the nitride material and the sidewall of the semiconductor substrate, wherein flowing the process gas includes flowing the process gas such that reactive nitrogen diffuses through the nitride material into at least one of a portion of the second barrier material and a portion of the first barrier material.

3. The method of claim 2 wherein the intermediary material comprises tantalum and tantalum nitride, and wherein the nitride material consists essentially of tantalum nitride.

4. The method of claim 2 wherein the intermediary material comprises titanium and titanium nitride.

5. The method of claim 1 wherein flowing the gas includes flowing the gas such that reactive nitrogen diffuses over an entire thickness of at least one of the first barrier material and the second barrier material.

6. The method of claim 1 wherein flowing the process gas includes flowing the process gas such that reactive nitrogen diffuses through the nitride material into at least one of a portion of the first barrier material and a portion of the second barrier material to form an intermediary region, wherein the intermediary region comprises a graded concentration of nitrided and unnitrided materials.

7. The method of claim 1 , further comprising depositing an insulator material over the sidewall of the semiconductor substrate, wherein depositing the second barrier material includes depositing the second barrier material over the insulator material.

8. The method of claim 1 wherein the second barrier material further comprises titanium, and wherein the nitride material comprises at least one of tantalum nitride and titanium nitride.

9. The method of claim 1 wherein the nitride material consists essentially of tantalum nitride, and wherein depositing the conductive material includes depositing the conductive material onto the tantalum nitride.

10. The method of claim 9 wherein depositing the conductive material includes depositing tantalum onto the tantalum nitride.

11. The method of claim 9 wherein depositing the conductive material includes depositing copper onto the tantalum nitride.

12. The method of claim 1 wherein the reactive nitrogen of the process gas comprises ionized ammonia.

13. A method of forming a through-silicon via (TSV), the method comprising:

forming an opening in a semiconductor substrate;

depositing a first unnitrided barrier material at least within the opening, wherein the first unnitrided barrier material comprises titanium;

depositing a second unnitrided barrier material over the first unnitrided barrier material, wherein the second unnitrided barrier material comprises tantalum, and wherein the second unnitrided barrier material has an exposed surface within the opening;

flowing a gas comprising reactive nitrogen to the exposed surface of the second unnitrided barrier to react the second unnitrided barrier material with the reactive nitrogen, wherein the second unnitrided barrier material is deposited over the first unnitrided barrier material before flowing the gas; and

at least partially filling the opening with a conductive material after flowing the gas.

14. The method of claim 13 wherein the second unnitrided barrier material consists essentially of tantalum, and wherein the method further comprises diffusing the reactive nitrogen into the tantalum to form tantalum nitride.

15. The method of claim 13 wherein the first unnitrided barrier material consists essentially of titanium, and wherein the method further comprises diffusing the reactive nitrogen into the titanium to form titanium nitride.

16. The method of claim 13 , further comprising forming an intermediary material between the nitrided barrier and a portion of the second unnitrided barrier material.

17. The method of claim 13 wherein the second unnitrided material further comprises titanium, and wherein the method further comprises diffusing the reactive nitrogen into the titanium to form titanium nitride.

18. A semiconductor device, comprising:

a semiconductor substrate having a surface, an opening in the surface, and a sidewall in the opening; and

an interconnect structure at least within the opening, wherein the interconnect structure includes:

a conductive material at least partially filling the opening, and

a nitrided barrier between the sidewall and the conductive material, wherein the nitrided barrier comprises:

a nitride material;

a first barrier material between the nitride material and the sidewall of the semiconductor substrate, wherein the first barrier material consists essentially of tantalum; and

a second barrier material between the first barrier material and the sidewall of the semiconductor substrate, wherein the second barrier material comprises titanium.

19. The semiconductor device of claim 18 wherein the nitride material consists essentially of tantalum nitride.

20. The semiconductor device of claim 19 wherein the nitrided barrier further comprises an intermediary region between the first barrier material and the nitride material, wherein the intermediary region comprises a graded concentration of tantalum and tantalum nitride.

21. The semiconductor device of claim 18 wherein the nitride material consists essentially of titanium nitride.

22. The semiconductor device of claim 18 wherein the interconnect structure includes a through-silicon via.

23. The semiconductor device of claim 18 wherein the semiconductor substrate comprises a memory circuit operably coupled to the interconnect structure.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: HERDT, GREGORY C.; TREGER, MIKHAIL A.; LU, JIN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041383/0854 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
Continuity (1)
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