Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors

1. An array of memory cells, individual of the memory cells comprising a vertical ferroelectric field effect transistor construction, the vertical field effect transistor comprising:

an isolating core;

a transition metal dichalcogenide material encircling the isolating core and having a lateral wall thickness of 1 monolayer to 7 monolayers;

a ferroelectric gate dielectric material encircling the transition metal dichalcogenide material;

conductive gate material encircling the ferroelectric gate dielectric material, the transition metal dichalcogenide material extending elevationally inward and elevationally outward of the conductive gate material; and

a conductive contact directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material.

2. The array of claim 1 wherein the isolating core, the transition metal dichalcogenide material, and the ferroelectric gate dielectric material each have a respective perimeter that is circular in horizontal cross-section.

3. The array of claim 1 wherein the transition metal dichalcogenide material is no greater than 4 monolayers in lateral wall thickness.

4. The array of claim 3 wherein the transition metal dichalcogenide material is no greater than 2 monolayers in lateral wall thickness.

5. The array of claim 1 wherein the transition metal dichalcogenide material comprises at least one of MoS 2 , WS 2 , InS 2 , MoSe 2 , WSe 2 , and InSe 2 .

6. The array of claim 1 wherein material of the conductive contact that is directly against the sidewall is elemental metal, an alloy of elemental metals, and/or a conductive metal compound.

7. The array of claim 1 wherein material of the conductive contact that is directly against the sidewall is conductively doped semiconductive material.

8. The array of claim 1 wherein the ferroelectric gate dielectric material has a lateral wall thickness of 1 nanometer to 30 nanometers.

9. The array of claim 8 wherein the ferroelectric gate dielectric material has a lateral wall thickness of 2 nanometers to 10 nanometers.

10. The array of claim 1 wherein the transition metal dichalcogenide material is no greater than 2 monolayers in lateral wall thickness, and the ferroelectric gate dielectric material has a lateral wall thickness of 2 nanometers to 10 nanometers.

11. The array of claim 1 wherein the conductive contact is directly against the lateral outer sidewall of the transition metal dichalcogenide material that is elevationally outward of the conductive gate material.

12. The array of claim 1 wherein the transition metal dichalcogenide material has an elevationally outermost end surface and an elevationally innermost end surface, the conductive contact not being directly against the one of said end surfaces that is most-proximate the lateral outer sidewall of the transition metal dichalcogenide material that the conductive contact is laterally directly against.

13. The array of claim 1 wherein the transition metal dichalcogenide material has an elevationally outermost end surface and an elevationally innermost end surface, the conductive contact also being directly against the one of said end surfaces that is most-proximate the lateral outer sidewall of the transition metal dichalcogenide material that the conductive contact is laterally directly against.

14. The array of claim 13 wherein sidewall-surface area of the transition metal dichalcogenide material that the conductive contact is directly against is greater than end wall-surface area of the transition metal dichalcogenide material that the conductive contact is directly against.

15. The array of claim 1 wherein the conductive contact is directly against the lateral outer sidewall of the transition metal dichalcogenide material that is elevationally inward of the conductive gate material.

16. The array of claim 1 wherein the conductive contact is directly against the lateral outer sidewall of the transition metal dichalcogenide material that is elevationally outward of the conductive gate material, and comprising another conductive contact that is directly against the lateral outer sidewall of the transition metal dichalcogenide material that is elevationally inward of the conductive gate material.

17. The array of claim 16 wherein the transition metal dichalcogenide material has an elevationally outermost end surface and an elevationally innermost end surface, the conductive contact not being directly against the outermost end surface, the another conductive contact not being directly against the innermost end surface.

18. The array of claim 16 wherein the transition metal dichalcogenide material has an elevationally outermost end surface and an elevationally innermost end surface, at least one of the conductive contact and the another conductive contact being directly against the elevationally outermost end surface or the elevationally innermost end surface, respectively.

19. The array of claim 18 wherein the conductive contact is directly against the elevationally outermost end surface and the another conductive contact is directly against the elevationally innermost end surface.

20. An array of memory cells, the memory cells comprising a vertical string of vertical ferroelectric field effect transistors, the vertical string of vertical ferroelectric field effect transistors comprising:

an isolating core;

a transition metal dichalcogenide material encircling the isolating core and having a lateral wall thickness of 1 monolayer to 7 monolayers;

a ferroelectric gate dielectric material encircling the transition metal dichalcogenide material;

alternating tiers of dielectric material and conductive gate material encircling the ferroelectric gate dielectric material, the transition metal dichalcogenide material and the ferroelectric material extending elevationally along the isolating core through the tiers, the transition metal dichalcogenide material extending elevationally beyond at least one of a) an elevationally outer of the conductive gate material tiers, and b) an elevationally inner of the conductive gate material tiers; and

a conductive contact directly against a lateral outer sidewall of the transition metal dichalcogenide material that is elevationally beyond a) the outer tier of the conductive gate material, or b) the inner tier of the conductive gate material.

21. The array of claim 20 comprising a NAND array of said vertical strings of vertical ferroelectric field effect transistors.

22. The array of claim 20 wherein the vertical string is a NAND string.

23. The array of claim 20 wherein the elevationally outer tier comprises the dielectric material.

24. The array of claim 23 wherein the transition metal dichalcogenide material extends elevationally beyond the elevationally outer of the dielectric material tiers.

25. The array of claim 20 wherein the elevationally inner tier comprises the dielectric material.

26. The array of claim 25 wherein the transition metal dichalcogenide material extends elevationally beyond the elevationally inner of the dielectric material tiers.