Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors
A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.
1. A construction comprising a pair of vertical ferroelectric field effect transistors, comprising:
isolating material laterally between a pair of vertical ferroelectric field effect transistors, the pair of transistors comprising:
a transition metal dichalcogenide film over each of two opposing lateral sides of the isolating material and individually having a lateral thickness of 1 monolayer to 7 monolayers;
a ferroelectric gate dielectric film laterally outward of each of the transition metal dichalcogenide films;
conductive gate material laterally outward of each of the ferroelectric gate dielectric films, the transition metal dichalcogenide films extending elevationally inward and elevationally outward of the conductive gate material on each of the two sides; and
a conductive contact directly against a lateral outer sidewall of each of the transition metal dichalcogenide films that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material.
2. The construction of claim 1 wherein the isolating material is dielectric.
3. The construction of claim 1 wherein the conductive contact is directly against the lateral outer sidewalls of the transition metal dichalcogenide material that is elevationally outward of the conductive gate material, and comprising another conductive contact that is directly against the lateral outer sidewall of each of the transition metal dichalcogenide films that are elevationally inward of the conductive gate material.
4. A vertical string of laterally opposing pairs of vertical ferroelectric field effect transistors, comprising:
alternating tiers of laterally opposing dielectric material and laterally opposing conductive gate material, the laterally opposing conductive gate material in individual of the tiers comprising a respective gate of one of a pair of laterally opposing vertical ferroelectric field effect transistors in that tier;
isolating material extending through the tiers laterally between the transistors of the respective pairs;
a transition metal dichalcogenide film extending through the tiers over each of two opposing lateral sides of the isolating material between the
isolating material and the laterally opposing conductive gate material, the transition metal dichalcogenide films individually having a lateral thickness of 1 monolayer to 7 monolayers;
the transition metal dichalcogenide films extending elevationally beyond at least one of a) an elevationally outer of the laterally opposing conductive gate material tiers, and b) an elevationally inner of the laterally opposing conductive gate material tiers;
a ferroelectric gate dielectric film extending through the tiers over each of two opposing lateral sides of the individual transition metal dichalcogenide films between the transition metal dichalcogenide films and the laterally opposing conductive gate material; and
a conductive contact directly against a lateral outer sidewall of a) each of the transition metal dichalcogenide films that is elevationally beyond the outer tier of the opposing conductive gate material, or b) each of the transition metal dichalcogenide films that is elevationally beyond the inner tier of the opposing conductive gate material.
5. The string of claim 4 comprising an array of said vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors.
6. The string of claim 5 wherein at least some immediately laterally adjacent of the vertical strings share a common horizontally extending line of the conductive gate material in individual of the tiers.
7. The construction of claim 1 wherein the conductive contact is directly against the lateral outer sidewalls of the transition metal dichalcogenide material that is elevationally outward of the conductive gate material.
8. The construction of claim 1 wherein the conductive contact is directly against the lateral outer sidewalls of the transition metal dichalcogenide material that is elevationally inward of the conductive gate material.
9. The construction of claim 1 wherein the transition metal dichalcogenide material is no greater than 4 monolayers in lateral wall thickness.
10. The construction of claim 9 wherein the transition metal dichalcogenide material is no greater than 2 monolayers in lateral wall thickness.
11. The construction of claim 1 wherein the transition metal dichalcogenide material comprises at least one of MoS 2 , WS 2 , InS 2 , MoSe 2 , WSe 2 , and InSe 2 .
12. The construction of claim 1 wherein material of the conductive contact that is directly against the sidewall is elemental metal, an alloy of elemental metals, and/or a conductive metal compound.
13. The construction of claim 1 wherein material of the conductive contact that is directly against the sidewall is conductively doped semiconductive material.
14. The construction of claim 1 wherein the ferroelectric gate dielectric material has a lateral wall thickness of 1 nanometer to 30 nanometers.
15. The construction of claim 14 wherein the ferroelectric gate dielectric material has a lateral wall thickness of 2 nanometers to 10 nanometers.
16. The construction of claim 1 wherein the transition metal dichalcogenide material is no greater than 2 monolayers in lateral wall thickness, and the ferroelectric gate dielectric material has a lateral wall thickness of 2 nanometers to 10 nanometers.
17. The construction of claim 1 wherein the transition metal dichalcogenide material has an elevationally outermost end surface and an elevationally innermost end surface, the conductive contact not being directly against the one of said end surfaces that is most-proximate the lateral outer sidewall of the transition metal dichalcogenide material that the conductive contact is laterally directly against.
18. The construction of claim 1 wherein the transition metal dichalcogenide material has an elevationally outermost end surface and an elevationally innermost end surface, the conductive contact also being directly against the one of said end surfaces that is most-proximate the lateral outer sidewall of the transition metal dichalcogenide material that the conductive contact is laterally directly against.