Memory arrays
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.
1. A memory array, comprising:
a semiconductor substrate;
a trench extending into the substrate and comprising an upper portion over a lower portion;
a liner along an interior wall of the lower and upper portions of the trench, the liner comprising a step at the transition between the lower portion and the upper portion;
a first electrically insulative material in the lower portion of the trench, the first electrically insulative material comprising a first composition that includes a void;
a second electrically insulative material in the upper portion of the trench, the second electrically insulative material comprising a second composition different from the first composition of the first electrically insulative material;
at least two transistors over the semiconductor substrate, the first and second electrically insulative materials electrically isolating the at least two transistors; and
wherein the liner is the only liner in the trench.
2. The memory array of claim 1 wherein the lower portion of the trench comprises a lateral width dimension that is less than a lateral width dimension of the upper portion of the trench.
3. The memory array of claim 1 wherein the liner comprises an upper section over a lower section, the upper section of the liner comprises a lateral width dimension that is less than a lateral width dimension of the lower section of the liner.
4. The memory array of claim 1 wherein an entirety of the liner comprises a single layer of material.
5. The memory array of claim 1 wherein an entirety of the liner comprises a single layer of material, and wherein the liner comprises an upper section over a lower section, the upper section of the liner comprises a lateral width dimension that is less than a lateral width dimension of the lower section of the liner.
6. The memory array of claim 1 wherein the void is devoid of the first electrically insulative material.
7. The memory array of claim 1 wherein the void comprises material that is different from the first electrically insulative material, the difference being one or more of phase, density, and chemical composition.
8. The memory array of claim 1 wherein the void comprises an ambient present during the forming of the first electrically insulative material.
9. The memory array of claim 1 wherein the void comprises gases outgassed from the first electrically insulative material.
10. The memory array of claim 1 wherein the first electrically insulative material defines the void.
11. The memory array of claim 1 wherein the lower portion of the trench is entirely defined by the liner that is single-layered structure and by the first electrically insulative material defining the void.
12. A memory array, comprising:
a semiconductor substrate;
a trench extending into the substrate and comprising an upper portion over a lower portion;
a liner along an interior wall of the lower and upper portions of the trench, the liner comprising a step at the transition between the lower portion and the upper portion;
a first electrically insulative material in the lower portion of the trench, the first electrically insulative material comprising a first composition that includes a void;
a second electrically insulative material in the upper portion of the trench, the second electrically insulative material comprising a second composition different from the first composition of the first electrically insulative material;
at least two transistors over the semiconductor substrate, the first and second electrically insulative materials electrically isolating the at least two transistors; and
wherein the first electrically insulative material defines the void.
13. A memory array, comprising:
a semiconductor substrate;
a trench extending into the substrate and comprising an upper portion over a lower portion;
a liner along an interior wall of the lower and upper portions of the trench, the liner comprising a step at the transition between the lower portion and the upper portion;
a first electrically insulative material in the lower portion of the trench, the first electrically insulative material comprising a first composition that includes a void;
a second electrically insulative material in the upper portion of the trench, the second electrically insulative material comprising a second composition different from the first composition of the first electrically insulative material;
at least two transistors over the semiconductor substrate, the first and second electrically insulative materials electrically isolating the at least two transistors; and
wherein the lower portion of the trench is entirely defined by the liner that is single-layered structure and by the first electrically insulative material defining the void.