Memory devices having source lines directly coupled to body regions and methods
View Patent ↗Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.
1. A memory device, comprising:
a data line;
a source;
a first string of memory cells coupled at a first end to the data line by a first select gate, and directly coupled at a second end to the source through a second select gate;
a second string of memory cells coupled at a first end to the data line by a third select gate, and directly coupled at a second end to the source through a fourth select gate; and
a controller, wherein the controller is configured to concurrently bias the data line and the source to substantially the same potential, and perform a program operation on a selected memory cell of the first string of memory cells.
2. The memory device of claim 1 , wherein the controller is further configured to bias the first select gate to a potential greater than the potential to which it concurrently biases the data line.
3. The memory device of claim 1 , wherein the first and the second strings of memory cells are vertically formed above a substrate.
4. A memory device, comprising:
a plurality of strings of memory cells, where each string of memory cells is coupled at a first end to a data line and where each string of memory cells is directly coupled at a second end to a source; and
a controller, wherein the controller is configured to concurrently bias the data line and the source to a substantially same potential and to perform a program operation on a selected memory cell of a selected string of memory cells while the data line and the source are biased to substantially the same potential.
5. The memory device of claim 4 , wherein the plurality of strings of memory cells comprise vertically formed strings of memory cells.
6. A memory device, comprising:
a plurality of strings of memory cells, where each string of memory cells is coupled at a first end to a data line and where each string of memory cells is directly coupled at a second end to a source; and
a controller, wherein the controller is configured to concurrently float the data line, bias the source to an erase potential, and perform an erase operation on the memory cells of the plurality of strings of memory cells.
7. The memory device of claim 6 , wherein the controller is further configured to bias a control gate of each memory cell of the plurality of strings of memory cells to a potential less than the erase potential to which the source is biased during the erase operation.
8. The memory device of claim 6 , wherein the potential to which the control gates of the memory cells are biased comprises a ground potential.
9. An electronic system, comprising:
a communications interface;
a memory access device coupled to the communications interface and configured to generate memory device commands; and
a memory device coupled to the communications interface and configured to be responsive to the memory device commands, the memory device comprising:
a data line;
a source;
a first string of memory cells coupled at a first end to the data line by a first select gate, and directly coupled at a second end to the source through a second select gate;
a second string of memory cells coupled at a first end to the data line by a third select gate, and directly coupled at a second end to the source through a fourth select gate; and
a controller, wherein the controller is configured to concurrently bias the data line and the source to substantially a same potential, and perform a program operation on a selected memory cell of the first string of memory cells.
10. The electronic system of claim 9 , wherein t S ring and the second string comprise vertically formed strings of memory cells.
11. A memory device, comprising:
an elongated body region, having a source region coupled to a first d and a drain region coupled to a second end;
a plurality of gates along a length of the elongated body region, each of the plurality f gates being separated from the elongated body region by at least a charge storage structure; and
a source line directly coupled to the body region, wherein the source region surrounds a cross section of the first end of the elongated body region and is also coupled to the source line.
12. The memory device of claim 11 , wherein the elongated body region oriented vertically.
13. The memory device of claim 11 , wherein the elongated body region is oriented horizontally.
14. The memory device of claim 11 , wherein the elongated body region forms a “U” shape.
15. The memory device of claim 11 , further including a controller, wherein the controller is configured to concurrently bias the data line and the source to substantially the same potential, and perform a program operation on a selected memory cell of the first string of memory cell.
16. The memory device of claim 11 , further including a controller, wherein the controller is configured to concurrently bias the data line and the source to a substantially same potential and to perform a program operation on a selected memory cell of a selected string of memory cells while the data line and the source are biased to substantially the same potential.
17. The memory device of claim 11 , further including a controller, wherein the controller is configured to concurrently float the data line, bias the source to an erase potential, and perform an erase operation on the memory cells of the plurality of strings of memory cells.