Transistors and methods of forming transistors

1. A transistor comprising:

a source region and a drain region; one of the source and drain regions being a hole reservoir region and the other being an electron reservoir region;

a gate between the source and drain regions;

first channel material between the gate and the source region; the first channel material being spaced from the gate by gate dielectric material; the gate dielectric material comprising silicon dioxide;

second channel material between the first channel material and the source region, the second channel material being spaced from the first channel material by tunnel dielectric material; and

wherein the first and second channel materials are transition metal dichalcogenide and/or transition metal trichalcogenide, and are different compositions relative to one another.

2. The transistor of claim 1 wherein the source and drain regions are the hole reservoir region and the electron reservoir region, respectively.

3. The transistor of claim 1 wherein the source and drain regions are the electron reservoir region and the hole reservoir region, respectively.

4. The transistor of claim 1 wherein the tunnel dielectric material comprises one or more oxides.

5. The transistor of claim 1 wherein the first channel material directly contacts the drain region.

6. The transistor of claim 1 wherein the first channel material does not directly contact the drain region.

7. The transistor of claim 1 wherein one of the first and second channel materials comprises a sulfide and the other comprises a selenide.

8. The transistor of claim 1 wherein one of the first and second channel materials comprises molybdenum sulfide and the other comprises tungsten selenide.

9. A transistor comprising:

a source region and a drain region; one of the source and drain regions being a hole reservoir region and the other being an electron reservoir region;

a gate between the source and drain regions;

first channel material between the gate and the source region; the first channel material being spaced from the gate by gate dielectric material;

second channel material between the first channel material and the source region, the second channel material being spaced from the first channel material by tunnel dielectric material;

wherein the first channel material does not directly contact the drain region; and

wherein an interconnect material extends from the drain region to the first channel material, the interconnect material comprising semiconductor material.

10. The transistor of claim 9 wherein the first and second channel materials are different compositions relative to one another.

11. The transistor of claim 9 wherein the first and second channel materials are transition metal dichalcogenide and/or transition metal trichalcogenide, and are different compositions relative to one another.

12. The transistor of claim 9 wherein the interconnect material comprises one or both of silicon and germanium; and wherein the interconnect material has no more than 1×10 14 atoms/cm 3 of conductivity-enhancing impurity therein.

13. The transistor of claim 12 wherein the interconnect material comprises silicon.

14. The transistor of claim 12 wherein the interconnect material comprises germanium.

15. The transistor of claim 12 wherein the interconnect material comprises silicon and germanium.

16. A memory array, comprising:

a plurality of transistors; each of the transistors comprising:

a source region spaced from a drain region; the source being a hole reservoir region and the drain region being an electron reservoir region;

a gate between the source and drain regions;

first channel material between the gate and the source region; the first channel material being spaced from the gate by gate dielectric material;

second channel material between the first channel material and the source region, the second channel material being spaced from the first channel material by tunnel dielectric material; and

the first and second channel materials being transition metal dichalcogenide and/or transition metal trichalcogenide, and being different compositions relative to one another; and

memory cells coupled with the source regions of each of the transistors.

17. The memory array of claim 16 wherein the memory cells are phase change memory cells.

18. The memory array of claim 16 wherein the memory cells are RRAM cells.

19. The memory array of claim 16 wherein the memory cells are magnetic RAM cells.

20. The memory array of claim 16 wherein the memory cells are conductive bridging RAM cells.

21. The memory array of claim 16 wherein the second channel material of each of the transistors is directly against the source region of each of the transistors.

22. The memory array of claim 16 wherein the first channel material of each of the transistors directly contacts the drain region of each of the transistors.

23. The memory array of claim 16 wherein the first channel material of each of the transistors does not directly contact the drain region each of the transistors.

24. The memory array of claim 23 wherein of each of the transistors includes an interconnect material which extends from the drain region of each of the transistors to the first channel material of each of the transistors; wherein the interconnect material comprises semiconductor material.

25. The memory array of claim 24 wherein the interconnect material of each of the transistors comprises one or both of silicon and germanium; and wherein the interconnect material of each of the transistors has no more than 1×10 14 atoms/cm 3 of conductivity-enhancing impurity therein.

26. The memory array of claim 25 wherein the interconnect material of each of the transistors comprises silicon.

27. The memory array of claim 25 wherein the interconnect material of each of the transistors comprises germanium.

28. The memory array of claim 25 wherein the interconnect material of each of the transistors comprises silicon and germanium.

29. The memory array of claim 25 being a first memory array within a first tier of a three-dimensional architecture; and wherein the three-dimensional architecture includes a second tier over said first tier; the second tier having a second memory array.

30. A memory array, comprising:

a plurality of transistors; each of the transistors comprising:

a source region spaced from a drain region; the source being a hole reservoir region and the drain region being an electron reservoir region;

a gate between the source and drain regions;

first channel material between the gate and the source region; the first channel material being spaced from the gate by gate dielectric material;

second channel material between the first channel material and the source region, the second channel material being spaced from the first channel material by tunnel dielectric material; and

the first and second channel materials being transition metal dichalcogenide and/or transition metal trichalcogenide, and being different compositions relative to one another; and

charge-storage devices coupled with the source regions of each of the transistors.

31. The memory array of claim 30 wherein the charge-storage devices are capacitors.

32. The memory array of claim 30 wherein the second channel material of each of the transistors is directly against the source region of each of the transistors.

33. The memory array of claim 30 wherein the first channel material of each of the transistors directly contacts the drain region of each of the transistors.

34. The memory array of claim 30 wherein the first channel material of each of the transistors does not directly contact the drain region of each of the transistors.

35. The memory array of claim 34 wherein an interconnect material extends from the drain region of each of the transistors to the first channel material of each of the transistors; wherein the interconnect material of each of the transistors comprises semiconductor material.

36. The memory array of claim 35 wherein the interconnect material of each of the transistors comprises one or both of silicon and germanium; and wherein the interconnect material of each of the transistors has no more than 1×10 14 atoms/cm 3 of conductivity-enhancing impurity therein.

37. The memory array of claim 36 wherein the interconnect material of each of the transistors comprises silicon.

38. The memory array of claim 36 wherein the interconnect material of each of the transistors comprises germanium.

39. The memory array of claim 36 wherein the interconnect material of each of the transistors comprises silicon and germanium.

40. The memory array of claim 30 being a first memory array within a first tier of a three-dimensional architecture; and wherein the three-dimensional architecture includes a second tier over said first tier; the second tier having a second memory array.