Transistors and methods of forming transistors

1. A transistor comprising:

a source region and a drain region; one of the source and drain regions being a hole reservoir region and the other being an electron reservoir region;

a gate between the source and drain regions, the gate comprising metal;

first channel material between the gate and the source region; the first channel material being spaced from the gate by one or more insulative materials;

second channel material between the first channel material and the source region, and directly contacting the source region; and

wherein the first and second channel materials are transition metal dichalcogenide and/or transition metal trichalcogenide, and are different compositions relative to one another.

2. The transistor of claim 1 wherein the source and drain regions are the hole reservoir region and the electron reservoir region, respectively.

3. The transistor of claim 1 wherein the source and drain regions are the electron reservoir region and the hole reservoir region, respectively.

4. The transistor of claim 1 further comprising tunnel dielectric material between the first and second channel materials.

5. The transistor of claim 1 wherein the first channel material directly contacts the drain region.

6. The transistor of claim 1 wherein the first channel material does not directly contact the drain region.

7. The transistor of claim 1 wherein one of the first and second channel materials comprises a sulfide and the other comprises a selenide.

8. The transistor of claim 1 wherein one of the first and second channel materials comprises molybdenum sulfide and the other comprises tungsten selenide.

9. A transistor comprising:

an electron reservoir drain region;

a gate over the drain region, the gate comprising metal;

bottom insulative material between the gate and the drain region, top insulative material over the gate, and sidewall insulative material along sidewalls of the gate and extending from a top of the gate to a bottom of the gate;

first channel material extending over the top insulative material, along the sidewall insulative material, and directly contacting the drain region; a region of the first channel material above the gate being a top region of the first channel material;

tunnel dielectric material over the top region of the first channel material;

second channel material over the tunnel dielectric material;

a hole reservoir source region directly against the second channel material; and

wherein the first and second channel materials are transition metal chalcogenide.

10. The transistor of claim 9 wherein the first and second channel materials are transition metal dichalcogenide and/or transition metal trichalcogenide.

11. The transistor of claim 9 wherein the first and second channel materials are different compositions relative to one another.

12. The transistor of claim 11 wherein the first channel material comprises a sulfide and the second channel material comprises a selenide.

13. The transistor of claim 11 wherein the first channel material comprises molybdenum sulfide and the second channel material comprises tungsten selenide.

14. The transistor of claim 9 wherein the bottom insulative material, top insulative material and sidewall insulative material are a same composition as one another.

15. The transistor of claim 9 wherein the bottom insulative material is a different composition than the top insulative material and sidewall insulative material.

16. A method of forming transistors, comprising:

forming a first stack comprising, an ascending order, digit line material, drain region material, first insulative material, and gate material;

patterning the first insulative material and gate material into pillars, and forming second insulative material along tops and sidewalls of the pillars;

after forming the second insulative material; utilizing the pillars as a mask during an etch through the drain region material; the etch forming the drain region material into pedestals beneath the pillars;

forming interconnecting material along sidewalls of the pillars and pedestals, and leaving gaps over regions of the digit line material between the pillars and pedestals;

filling the gaps with third insulative material and planarizing a top surface across the second insulative material, interconnecting material and third insulative material;

forming a second stack over the planarized top surface; the second stack comprising, in ascending order, first channel material, tunnel dielectric material, second channel material and source region material; and

forming openings through the second stack to the third insulative material.

17. The method of claim 16 wherein the first and second channel materials are transition metal chalcogenide.

18. The method of claim 16 wherein the interconnecting material is a same composition as the first channel material.

19. The method of claim 16 wherein the interconnecting material is a different composition than the first channel material.

20. The method of claim 19 wherein the interconnecting material comprises undoped semiconductor material.

21. The method of claim 19 wherein the interconnecting material comprises undoped silicon.

22. The method of claim 16 wherein the first and second channel materials are transition metal dichalcogenide and/or transition metal trichalcogenide.

23. The method of claim 16 wherein the first and second channel materials are different compositions relative to one another.

24. The method of claim 23 wherein the first channel material comprises a sulfide and the second channel material comprises a selenide.

25. The method of claim 23 wherein the first channel material comprises molybdenum sulfide and the second channel material comprises tungsten selenide.