Integrated circuitry and methods of forming transistors
Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.
1. A method of forming transistors, comprising:
forming an active area of a first transistor, the first transistor comprising a gate and source/drain regions;
forming an active area of a second transistor, the second transistor comprising a gate and source/drain regions, wherein a length dimension for first and second transistors is defined in a direction along a dimension of spacing distance between respective source/drain regions of each transistor and a width dimension is perpendicular to the length dimension, where the active area of the first transistor is wider (in the direction of the width dimension) than the active area of the second transistor;
forming first dielectric features in the active area of the first transistor to break up the active area of the first transistor to a first extent, the first dielectric features are spaced, in the direction of the length dimension, from the gate and the source/drain regions in the active area of the first transistor;
forming second dielectric features in the active area of the second transistor to break up the active area of the second transistor to a second extent which is different than the first extent; the first and second dielectric features comprising a same composition; and
after forming the first and second dielectric features, doping the active area of the first transistor and the active area of the second transistor with a same dopant concentration.
2. The method of claim 1 wherein the first dielectric features are two or more features with length greater than width.
3. The method of claim 2 wherein the source/drain region is a drain region.
4. The method of claim 1 wherein the first dielectric features are arranged on both sides of a gate of said first transistor, with the first dielectric features on one side of the gate being a mirror image of the first dielectric features on an opposing side of the gate.
5. The method of claim 1 wherein the first dielectric features are not symmetrically distributed on one side of the gate relative to another side of the gate.
6. The method of claim 1 wherein the first and second transistors are high-voltage transistors.
7. The method of claim 6 wherein a memory array is formed proximate the high-voltage transistors and is electrically coupled with the high-voltage transistors.
8. The method of claim 7 wherein the memory array comprises flash memory devices, and further comprising utilizing the high-voltage transistors during a block erase of the flash memory devices.
9. The method of claim 1 wherein the second dielectric features are spaced, in the direction of the length dimension, from the gate and the source/drain regions in the active area of the second transistor.
10. The method of claim 1 wherein at least one of the first dielectric features are shaped, in the plan view (horizontal plane), in at least one of the following shapes: square, circular, oval, elliptical and/or curved.
11. The method of claim 1 wherein the first dielectric features are rectangularly shaped with the greater dimension of the rectangular shape being in the direction of the length dimension of the first transistor.
12. The method of claim 1 wherein the first dielectric features are rectangularly shaped and the gate is rectangularly shaped, the greater dimensions of respective rectangular shapes are perpendicular relative to each other.
13. The method of claim 1 wherein at least two of the first dielectric features are differently shaped relative to each other.
14. The method of claim 1 wherein the first dielectric features are configured as a first shape, wherein the second dielectric features are configured as a second shape, the first shape and the second shape are different shapes.
15. The method of claim 1 wherein a spacing between at least two of the first dielectric features comprises a first dimension, wherein a spacing between at least two of the second dielectric features comprises a second dimension, the first dimension and the second dimension are different dimensions.
16. The method of claim 1 wherein the active area of the first transistor is broken up to a first degree by the first dielectric features, wherein the active area of the second transistor is broken up to a second degree by the second dielectric features, the first degree and the second degree are different degrees.