Methods of forming transistors with broken up active regions
Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.
1. A method of forming transistors of different widths, comprising:
forming an active area of a first transistor;
forming an active area of a second transistor, where the active area of the first transistor is wider than the active area of the second transistor;
forming first dielectric features in the active area of the first transistor to break UP the active area of the first transistor to a first extent;
forming second dielectric features in the active area of the second transistor to break UP the active area of the second transistor to a second extent which is different than the first extent; and
after forming the first and second dielectric features, doping the active area of the first transistor and the active area of the second transistor with a same dopant concentration.
2. The method of claim 1 wherein the first dielectric features are two or more features with length greater than width, that extend between a gate of said first transistor and a source/drain region of said first transistor.
3. The method of claim 2 wherein the source/drain region is a drain region.
4. The method of claim 1 wherein the first dielectric features are arranged on both sides of a gate of said first transistor, with the first dielectric features on one side of the gate being a mirror image of the first dielectric features on an opposing side of the gate.
5. The method of claim 1 wherein said first transistor has a gate, and where the first dielectric features are not symmetrically distributed on one side of the gate relative to another side of the gate.
6. The method of claim 1 wherein the first and second transistors are both high-voltage transistors.
7. The method of claim 6 wherein a memory array is formed proximate the high-voltage transistors and is electrically coupled with the high-voltage transistors.
8. The method of claim 7 wherein the memory array comprises flash memory devices, and further comprising utilizing the high-voltage transistors during a block erase of the flash memory devices.
9. A method of forming transistors of different widths, comprising:
forming an active area of a first transistor;
forming an active area of a second transistor, where the active area of the first transistor is wider than the active area of the second transistor;
forming first dielectric features in the active area of the first transistor and second dielectric features in the active area of the second transistor, where the active areas of the first and second transistors are broken UP by the first and second dielectric features, and where the active area of the first transistor is broken up to a different extent than the active area of the second transistor; and
simultaneously doping the active area of the first transistor and the active area of the second transistor with a single implant.
10. The method of claim 9 wherein the transistors are high-voltage transistors.