Integrated circuitry and methods of forming transistors
Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.
1. An integrated circuit, comprising:
first, second and third transistors supported by a silicon-containing substrate;
the first transistor being wider than the second transistor;
the first and second transistors comprising first and second active regions, respectively; dielectric features being associated with the first active region and breaking up the first active region; the second active region not being broken up to the same extent as the first active region; and
the third transistor being wider than the first transistor; dielectric features being associated with the third active region and breaking up the third active region; the third active region being broken up to a different extent than the first active region.
2. The integrated circuit of claim 1 wherein the first, second and third transistors are high-voltage transistors.
3. The integrated circuit of claim 1 wherein the first, second and third transistors are electrically coupled to a memory array.
4. The integrated circuit of claim 1 further comprising a fourth transistor less wide than the second transistor and comprising a fourth active region; and wherein the fourth active region is not broken up.
5. The integrated circuit of claim 1 wherein the dielectric features associated with the first active region are first dielectric features, and wherein the first dielectric features are arranged on both sides of a gate of the first transistor, with the first dielectric features on one side of the gate being a mirror image of the first dielectric features on an opposing side of the gate.
6. The integrated circuit of claim 1 wherein the dielectric features associated with the first active region are first dielectric features, and wherein the first dielectric features are not symmetrically distributed on one side of a gate of the first transistor relative to an opposing side of the gate.