Data shift apparatuses and methods

1. An apparatus, comprising:

a memory device, comprising:

an array of memory cells;

sensing circuitry coupled to the array via a plurality of sense lines;

a first shared I/O line configured to selectably couple a first subset of the plurality of sense lines and a second shared I/O line configured to selectably couple a second subset of the plurality of sense lines;

a shift element configured to selectably couple the first shared I/O line to the second shared I/O line to enable a data shift operation; and

a controller configured to direct selectable coupling of the array, the sensing circuitry, and the shift element to enable a shift of a data value from the first shared I/O line to the second shared I/O line.

2. The apparatus of claim 1 , wherein the data shift operation comprises:

a plurality of data values each stored in a first portion of a row, as a source location, by a corresponding plurality of memory cells coupled to a corresponding number of sense lines that are selectably coupled to the first shared I/O line;

the shift element coupling the first shared I/O line to the second shared I/O line; and

movement of the plurality of data values to a corresponding plurality of memory cells in a second portion of the row, as a destination location, coupled to a corresponding number of sense lines selectably coupled to the second shared I/O line; and

wherein the data shift operation further comprises a similar data shift operation performed by movement of data values each stored in the second portion of the row to a corresponding plurality of memory cells in a third portion of the row.

3. The apparatus of claim 1 , wherein:

the sensing circuitry comprises a sense amplifier or a compute component coupled to a particular sense line; and

the sensing circuitry is configured to couple a particular subset of sense lines to a particular shared I/O line in order to implement the data shift operation.

4. The apparatus of claim 1 , wherein the sensing circuitry is formed on pitch with complementary sense lines for corresponding complementary memory cells of a dynamic random access memory (DRAM) array.

5. The apparatus of claim 1 , wherein the shift element comprises:

a latch configured to receive a data value via a first shared I/O line and configured to send the data value via a second shared I/O line to perform the data shift operation; and

a select element configured to enable the data value to be selectably received from a particular first shared I/O line and selectably sent to a particular second shared I/O line.

6. The apparatus of claim 5 , wherein the select element comprises:

first select circuitry configured to selectably receive a data value from a source location via the particular first shared I/O line selected from a plurality of shared I/O lines; and

second select circuitry configured to selectably send the data value to a destination location via the particular second shared I/O line selected from the plurality of shared I/O lines.

7. The apparatus of claim 1 , wherein the shift element is circuitry separate from the sensing circuitry.

8. The apparatus of claim 1 , wherein the shift element is formed on pitch with the sense lines and the memory cells of the array.

9. The apparatus of claim 1 , wherein the shift element is:

formed on chip with and on a different plane than the first shared I/O line, the second shared I/O line, and the memory cells of the array; and

further configured to couple the first shared I/O line at a first node and to couple the second shared I/O line at a second node.

10. The apparatus of claim 1 , wherein:

the shift element is further configured to selectably couple the first shared I/O line of the first subset of the plurality of sense lines to the second shared I/O line of the second subset of the plurality of sense lines and to a third shared I/O line of a third subset of the plurality of sense lines; and

the second shared I/O line is offset relative to the first shared I/O line in a direction opposite from an offset of the third shared I/O line relative to the first shared I/O line.

11. An apparatus, comprising:

a memory device, comprising:

an array of memory cells;

sensing circuitry coupled to the array via a plurality of sense lines;

a plurality of shared I/O lines each configured to selectably and bidirectionally move a data value within the array; and

a pair of shift elements comprising a first shift element and a second shift element, wherein each shift element in the pair is configured to:

couple a particular shared I/O line of the respective plurality of shared I/O lines selectably to a first shared I/O line and a second shared I/O line; and

shift the data value from a coupled first shared I/O line, offset in a first direction by a span of shared I/O lines from the particular shared I/O line, to the second shift element coupled to a second shared I/O line offset in a second direction by the span of shared I/O lines from the particular shared I/O line; and

a controller configured to direct selectable coupling of the array, the sensing circuitry, and the first and second shift elements to enable an operation to shift a data value from the first shared I/O line to the second shared I/O line.

12. The apparatus of claim 11 , wherein:

the first shift element is positioned adjacent the first shared I/O line and is configured to:

read the data value from the coupled first shared I/O line offset in the first direction;

write the data value to the second shift element coupled to the second shared I/O line offset in the second direction in order to perform the data shift operation; and

wherein the read operation and the write operation are performed in different clock cycles.

13. The apparatus of claim 11 , wherein:

the span is a same number of shared I/O lines in the first direction and the second direction by which the first shared I/O line and the second shared I/O line are offset from the particular shared I/O line.

14. The apparatus of claim 11 , wherein:

the first shift element is further configured to:

selectably couple the first shared I/O line as a source to shift the data value across the span to the first shift element; and

shift the data value across the span to the second shared I/O line; and

the second shift element is further configured to:

selectably couple the second shared I/O line to receive movement of the data value across the span as a first destination; and

selectably couple a third shared I/O line to shift the data value across the span to a third shift element as a second destination.

15. The apparatus of claim 11 , wherein the memory device further comprises:

a plurality of subarrays in the array of memory cells; and

a plurality of shared I/O lines each configured to selectably and bidirectionally move a data value within and between the respective plurality of subarrays; and

wherein the data shift operation is performed in a first subarray and a data source location and a data destination location are in a second subarray.

16. The apparatus of claim 15 , wherein:

the second subarray is a subarray for the data source location that is different from a subarray for the data destination location.

17. An apparatus, comprising:

a controller coupled to a memory device and configured to direct a data shift operation, wherein the memory device comprises:

an array of memory cells;

sensing circuitry coupled to the array via a plurality of columns of the memory cells, the sensing circuitry including a sense amplifier or a compute component coupled to each of the columns and configured to implement a command from the controller to shift data values;

a plurality of shared I/O lines each configured to selectably and bidirectionally move a data value within the array; and

a pair of a first shift element and a second shift element, wherein each shift element in the pair is configured to:

shift the data value from a coupled first shared I/O line, offset in a first direction by a span of shared I/O lines, to the second shift element coupled to a second shared I/O line offset in a second direction by the span of shared I/O lines.

18. The apparatus of claim 17 , wherein the span is a multiple of 64 shared I/O lines.

19. The apparatus of claim 17 , wherein:

the second shared I/O line is positioned between the first shared I/O line and a third shared I/O line; and

the first shared I/O line and the third shared I/O line are each separated from the second shared I/O line by at least one intervening shared I/O line.

20. The apparatus of claim 17 , wherein the controller is further configured to:

selectably couple the first shift element to the first shared I/O line and the second shared I/O line via connection circuitry that extends in the first direction and the second direction; and

wherein the connection circuitry couples the first shift element to the first shared I/O line at a first node and couples the first shift element to the second shared I/O line at a second node.

21. The apparatus of claim 17 , wherein the memory device further comprises:

the first shift element and the second shift element configured as the pair positioned adjacent each of the respective plurality of shared I/O lines;

a plurality of first shift elements configured as a first set positioned toward a first end of the respective plurality of shared I/O lines; and

a plurality of second shift elements configured as a second set positioned toward a second end of the respective plurality of shared I/O lines; and

wherein to shift the data value comprises to move the data value between the first set of shift elements and the second set of shift elements along a length of at least one of the respective plurality of shared I/O lines.

22. The apparatus of claim 21 , wherein the controller is further configured to:

issue a single set of first control signals to direct the plurality of first shift elements of the first set to shift a respective plurality of data values to a corresponding plurality of the second shift elements of the second set; and

issue a single set of second control signals to direct the plurality of second shift elements of the second set to shift a respective plurality of data values to a corresponding plurality of the first shift elements of the first set; and

wherein the first control signals are different from the second control signals based upon a differential of read operations and write operations being performed by the first set and the second set.

23. The apparatus of claim 21 , wherein the controller is further configured to:

selectably couple the first shift element to the second shared I/O line offset in the second direction by the span of shared I/O lines;

selectably couple the second shift element to the second shared I/O line offset in the first direction by the span of shared I/O lines; and

shift a data value a distance of two spans from the first shift element to the second shift element.

24. The apparatus of claim 23 , wherein:

the first shift element is adjacent and selectably coupled to a particular shared I/O line in the first direction from the second shared I/O line;

the second shift element is adjacent and selectably coupled to a different shared I/O line in the second direction from the second shared I/O line; and

the particular shared I/O line and the different shared I/O line are separated by the distance of two spans.

25. The apparatus of claim 23 , wherein:

the first shift element is positioned toward one end of a particular shared I/O line in the first direction from the second shared I/O line;

the second shift element is positioned toward an opposite end of a different shared I/O line in the second direction from the second shared I/O line; and

the controller is further configured to shift the data value along a length of the second shared I/O line to shift the data value the distance of two spans from the first shift element to the second shift element; and

the first shift element and the second shift element are both coupled to the second shared I/O line.

26. The apparatus of claim 21 , wherein:

a particular first shift element of the first set is configured to selectably couple the second shared I/O line offset in the second direction by the span to shift a data value;

a particular second shift element of the second set is configured to store the shifted data value received via the second shared I/O line; and

the controller is further configured to:

move the data value along a length of the second shared I/O line to the particular second shift element of the second set;

couple a different first shift element of the first set to the second shared I/O line offset in the first direction by the span to access the data value stored by the particular second shift element; and

move the data value along the length of the second shared I/O line to the different first shift element of the first set to shift the data value a distance of two spans.

27. The apparatus of claim 26 , wherein the sensing circuitry comprises the second set of second shift elements.

28. The apparatus of claim 17 , wherein the memory device further comprises:

the first shift element and the second shift element configured as the pair positioned toward one end of each of the respective plurality of shared I/O lines; and

wherein to shift the data value comprises to shift the data value from a first pair of shift elements positioned toward the end of a first shared I/O line via connection circuitry coupled to a second pair of shift elements positioned toward the end of a second shared I/O line.

29. A method for operating a memory device, comprising:

receiving control signals from a controller coupled to an array of memory cells that direct moving a data value from a source location to a destination location in the array;

selectably coupling a first shift element to a first shared I/O line;

moving the data value from the first shared I/O line as the source location to the first shift element;

selectably coupling a second shift element to a second shared I/O line; and

moving the data value from the second shift element to the second shared I/O line.

30. The method of claim 29 , wherein the method further comprises:

offsetting the first shift element from the first shared I/O line in a first direction by a span of shared I/O lines; and

offsetting the second shift element from the second shared I/O line in a second direction by the span of shared I/O lines.

31. The method of claim 29 , wherein the method further comprises:

moving the data value a distance of two spans from the first shared I/O line as the source location to the second shared I/O line as the destination location.

32. The method of claim 29 , wherein the controller is configured to direct:

moving the data value an even number of spans from the source location to the destination location.

33. The method of claim 29 , wherein the controller is configured to direct:

moving the data value by a single-bit shift operation to an odd-numbered span to which the data value is to be shifted; and

moving the data value utilizing sensing circuitry of the array to perform the single-bit shift operation via connection circuitry that connects adjacent shift elements from an even-numbered span to the odd-numbered span.

34. The method of claim 29 , wherein the controller is configured to direct:

selecting, by execution of stored instructions, between a number of shifts of the data value from the source location to the destination location; and

wherein the number of shifts include:

a number of shifts across a number of spans when the source location and the destination location are separated by the number of spans;

a number of shifts across a number of spans and a number of single-bit shift operations when the source location and the destination location are separated by the number of spans;

a number of shifts across a number of spans when the source location and the destination location are partially separated by a number of spans and a number of single-bit shift operations when a remainder of a separation between the source location and the destination location is a portion of a span; and

a number of single-bit shift operations selectably performed before, between, or after performance of a number of shifts across a number of spans.

35. The method of claim 34 , wherein selecting between the number of shifts comprises selecting based on:

a distance between the source location and the destination location;

a length of a bit vector;

whether the bit vector is to be shifted and rotated; and

whether an input from the source location and an output of the bit vector to the destination location are in a same subarray, partition, or bank of the memory device.

36. The method of claim 29 , wherein the controller is configured to direct:

rotating the data value from a first shared I/O line at one end of the array via rotation circuitry to a second shared I/O line at an opposite end of the array; and

wherein data values stored by memory cells selectably coupled to the second shared I/O line have been shifted by a data shift operation inward from the opposite end of the array to a destination location.

37. The method of claim 29 , wherein the controller is configured to direct:

masking a particular portion of the array to prevent writing a shifted data value to a number of shift elements in the particular portion.

38. The method of claim 29 , wherein the controller is configured to direct:

clearing a particular portion of the array to prevent overwriting a shifted data value to a number of memory cells selectably coupled to shift elements and shared I/O lines in the particular portion; and

wherein cleared data values are moved to another portion of the array.