Memory management

1. An apparatus, comprising:

a first memory array, wherein the first memory array includes a first plurality of managed units;

a number of second memory arrays, wherein the second memory array includes a second plurality of managed units; and

a controller coupled to the first memory array and the number of second memory arrays configured to:

execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor; and

place the write cursor at an updated location in the first memory array, wherein placing the write cursor in the updated location is determined by a status of the first plurality of managed units and the write cursor is placed in a next available location in the first memory array where a next one of the first plurality of managed unit indicates a free status upon completing execution of the write operation.

2. The apparatus of claim 1 , wherein execution of the write operation also writes the data to the number of second arrays.

3. The apparatus of claim 1 , wherein the write operation is a foreground operation that is completed by the apparatus upon receiving a request.

4. The apparatus of claim 1 , wherein the first memory array includes a number of managed units that are assigned addresses sequentially and wherein data is written sequentially to the number of managed units based on the assigned addresses and the location of the write cursor.

5. The apparatus of claim 1 , wherein the controller is configured to execute another write operation and wherein execution of the another write operation writes data to the first memory array starting at the updated location indicated by the write cursor.

6. The apparatus of claim 1 , wherein the write cursor is placed at the updated location by skipping a number of managed units that are indicated as valid, invalid, or do not use to find a next free managed unit in the first memory array.

7. The apparatus of claim 1 , wherein execution of the write operation includes continuing to write the data to the first memory array in a number of free managed units sequentially until the write operation is complete based on addresses of the number of free managed units.

8. The apparatus of claim 1 , wherein the first memory array is a storage class memory and the number of second arrays are NAND Flash memory arrays.

9. An apparatus, comprising:

a first memory array;

a number of second memory arrays; and

a controller coupled to the first memory array and to the number of second memory arrays and configured to:

set a number of read signals based on a read managed unit pattern;

perform a read operation on data at a managed unit in the first memory array using the number of read signals to determine a managed unit pattern disturb level and/or a raw bit error rate (RBER) for the data;

output the data to a host in response to the RBER being below a first threshold and/or the managed unit pattern disturb level being below a second threshold; and

perform a move operation on the data in response to the RBER being above the first threshold and/or the managed unit pattern disturb level being above the second threshold.

10. The apparatus of claim 9 , wherein the managed unit pattern disturb level is based on a number of times that a neighboring managed unit has been programmed.

11. The apparatus of claim 9 , wherein the move operation relocates the data by writing the data to a new managed unit that is free in the first memory array.

12. The apparatus of claim 9 , wherein the controller is configured to output the data after performing the move operation by reading the data from the new managed unit.

13. The apparatus of claim 9 , wherein the controller is configured to indicate that the managed unit is invalid in response to the RBER being above the first threshold and/or the managed unit pattern disturb level being above the second threshold.

14. A method for managing memory, comprising:

performing a write operation starting at a location in a first memory array indicated by a write cursor, wherein the write cursor is at a managed unit that is in a free state; and

placing the write cursor at an updated location in the first memory array upon completion of the write operation, wherein placing the write cursor in the updated location is determined by a status of the managed unit and the write cursor is placed in a next available location in the first memory array where a next one of managed unit indicates a free status upon completing execution of the write operation.

15. The method of claim 14 , wherein placing the write cursor at the updated location includes locating a next free managed unit in the first memory array.

16. The method of claim 14 , wherein placing the write cursor at the updated location includes skipping a number of managed units that are in a valid, invalid, or do not use state.

17. The method of claim 14 , wherein the method includes performing a clean operation on a number of managed units that were in an invalid state in the first memory array by placing the number of managed units in a free state.

18. The method of claim 14 , wherein the method includes performing another write operation starting at the updated location of the write cursor.

19. A method for managing memory, comprising:

determining a managed unit pattern disturb level and/or a raw bit error rate (RBER) for data at a managed unit in a first memory array;

outputting the data to a host in response to the RBER being below a first threshold and/or the managed unit pattern disturb level being below a second threshold; and

performing a move operation on the data in response to the RBER being above the first threshold and/or the managed unit pattern disturb level being above the second threshold.

20. The method of claim 19 , wherein the method includes performing the move operation only while no other operations are being performed on a particular area where the move operation is being performed.

21. The method of claim 19 , wherein performing the move operation includes writing the data to a free managed unit in the first memory array.

22. The method of claim 19 , wherein determining the managed unit pattern disturb level includes determining a number of times that a number of neighboring managed units have been programmed.