Secure subsystem
View Patent ↗An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.
1. An apparatus comprising:
a memory device located within a secure boundary and configured to store one or more secret data objects;
a processor located within the secure boundary and configured to execute security firmware and perform a set of operations limited to a plurality of secure operations for manipulating the one or more secret data objects;
a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the plurality of secure operations; and
one or more security assist hardware circuits configured to perform discrete operations using the one or more secret data objects, wherein each of the plurality of secure hardware registers corresponds to a different security assist hardware circuit, the discrete operations comprising at least one of data encryption, data decryption, signature calculation and checking, and random number generation.
2. The apparatus of claim 1 , further comprising:
security firmware stored on a memory device and defining a plurality of operations executable by the processor for manipulating one or more secret data objects.
3. The apparatus of claim 1 , wherein the one or more secret data objects comprise at least one encryption key.
4. The apparatus of claim 1 , further comprising:
an encrypt circuit configured to receive a plurality of data and encrypt the plurality of data based on one or more secret data objects.
5. An apparatus comprising:
an internal memory device for storing one or more secret data objects;
one or more secure hardware registers configured to receive a command to perform an operation using the one or more secret data objects; and
one or more security assist hardware circuits configured to perform discrete operations using the one or more secret data objects, wherein each of the one or more secure hardware registers corresponds to a different security assist hardware circuit, the discrete operations comprise at least one of random number generation, encryption key generation, signature calculation, signature verification, symmetric encryption, symmetric decryption, asymmetric encryption, and asymmetric decryption.
6. The apparatus of claim 5 , wherein the secret data objects are inaccessible to devices outside of the apparatus.
7. The apparatus of claim 5 , wherein the commands are received from a system processor executing security firmware stored on a memory external to the apparatus.
8. An apparatus comprising:
a secure subsystem configured to perform one or more secure operations involving one or more secret data objects, wherein the secure subsystem comprises:
a secure processor configured to execute security firmware and perform a set of operations limited to a plurality of secure operations for manipulating one or more secret data objects;
a plurality of secure hardware registers, accessible by the secure processor and configured to receive instructions to perform the plurality of secure operations; and
one or more security assist hardware circuits configured to perform discrete operations using the one or more secret data objects, wherein each of the plurality of secure hardware registers corresponds to a different security assist hardware circuit, the discrete operations comprise at least one of random number generation, encryption key generation, signature calculation, signature verification, symmetric encryption, symmetric decryption, asymmetric encryption, and asymmetric decryption; and
a memory access circuit configured to request that the secure subsystem perform the plurality of secure operations.
9. The apparatus of claim 8 , further comprising:
one or more storage devices configured to store the one or more secret data objects.
10. The apparatus of claim 8 , wherein the secure subsystem comprises:
security firmware stored on one or more memory devices and configured to control performance of the plurality of secure operations.
11. The apparatus of claim 8 , wherein the memory access circuit comprises:
a system processor configured to request that the secure subsystem perform the plurality of secure operations.
12. The apparatus of claim 11 , wherein the secure subsystem comprises:
storage system firmware for execution by the system processor and configured to control the request that the secure subsystem perform the plurality of secure operations.
13. The apparatus of claim 8 , wherein the secure subsystem comprises:
an encryption circuit configured to encrypt data using the one or more secret data objects; and
a decryption circuit configured to decrypt data using the one or more secret data objects.
14. A method comprising:
receiving, at one or more of a plurality of secure hardware registers, a request to execute a secure operation using one or more secret data objects;
executing, with one of a plurality of security assist hardware circuits, the secure operation, the secure operation comprising at least one of random number generation, encryption key generation, signature calculation, signature verification, symmetric encryption, symmetric decryption, asymmetric encryption, and asymmetric decryption, wherein each secure hardware register of the plurality of secure hardware registers corresponds to a different security assist hardware circuit; and
transmitting to an unsecure hardware register, a value responsive to executing the secure operation, wherein
the secure hardware register, the one or more secret data objects, and a dedicated secure processor are located within a secure boundary.
15. The method of claim 14 , further comprising:
notifying the dedicated secure processor of the received request to execute the secure operation.
16. The method of claim 14 , wherein the dedicated secure processor executes the secure operation based on dedicated security firmware stored on a memory device within the secure boundary.
17. The method of claim 16 , wherein the dedicated security firmware defines a limited number of secure operations.
18. The method of claim 14 , wherein executing the secure operation comprises:
encrypting data using the one or more secret data objects; and
storing the encrypted data in a storage device external to the secure boundary.
19. The method of claim 14 , wherein executing the secure operation comprises:
retrieving encrypted data from a storage device external to the secure boundary; and
decrypting the encrypted data using the one or more secret data objects.
20. An apparatus comprising:
a memory access circuit configured to receive instructions to perform memory operations, wherein at least one of the memory operations manipulates a secret data object; and
a secure subsystem circuit configured to receive instructions from the memory access circuit to perform the at least one memory operation by manipulating the secret data object, wherein the secure subsystem circuit comprises:
a plurality of secure hardware registers configured to receive the instructions from the memory access circuit; and
a plurality of security assist hardware circuits configured to perform discrete operations using the one or more secret data object, wherein each of the one or more secure hardware registers corresponds to a different security assist hardware circuit, the discrete operations comprise at least one of random number generation, encryption key generation, signature calculation, signature verification, symmetric encryption, symmetric decryption, asymmetric encryption, and asymmetric decryption.
21. The apparatus of claim 20 , wherein the secure subsystem circuit comprises a processor for performing a limited number of operations, wherein the limited number of operations includes the at least one memory operation manipulating the secret data object.
22. A method comprising:
receiving at one or more of a plurality of secure hardware registers located within a secure boundary of an integrated circuit, a request to execute a secure operation involving one or more secret data objects;
identifying one or more of a plurality of security assist hardware circuits configured to execute the secure operation, wherein each of the one or more secure hardware registers corresponds to a different security assist hardware circuit; and
executing the secure operation using the one or more identified security assist hardware circuits, the secure operation comprising at least one of random number generation, encryption key generation, signature calculation, signature verification, symmetric encryption, symmetric decryption, asymmetric encryption, and asymmetric decryption.
23. The method of claim 22 , further comprising:
transmitting to an unsecure hardware register, a value responsive to executing the secure operation, wherein
the one or more secure hardware registers, the one or more secret data objects, and the dedicated secure processor are stored on a memory within a secure boundary.
24. The method of claim 22 , wherein the one or more secret data objects comprise one or more encryption keys.
25. The method of claim 22 , wherein the request is received from a memory system processor executing security firmware.