Memory arrays comprising ferroelectric capacitors
Some embodiments include a memory array which has rows of fins. Each fin has a first pedestal, a second pedestal and a trough between the first and second pedestals. A first source/drain region is within the first pedestal, a second source/drain region is within the second pedestal, and a channel region is along the trough between the first and second pedestals. Digit lines are electrically coupled with the first source/drain regions. Ferroelectric capacitors are electrically coupled with the second source/drain regions. Wordlines are along the rows of fins and overlap the channel regions. Conductive isolation lines are under the wordlines along the rows of fins.
1. A memory array, comprising:
rows of fins; each fin having a first pedestal, a second pedestal and a trough between the first and second pedestals; a first source/drain region being within the first pedestal, a second source/drain region being within the second pedestal, and a channel region being along the trough between the first and second pedestals;
digit lines electrically coupled with the first source/drain regions;
ferroelectric capacitors electrically coupled with the second source/drain regions;
wordlines along the rows of fins and overlapping the channel regions; and
conductive isolation lines under the wordlines along the rows of fins.
2. The memory array of claim 1 wherein each row of fins has a first side and a second side; the wordlines gating each row from both of the first and second sides.
3. The memory array of claim 2 wherein each of the wordlines comprise a pair of wordline components, with one component of said pair extending along the first side of a row of fins and the other component of said pair extending along the second side of the row of fins; and wherein the wordline components comprise metal.
4. The memory array of claim 1 wherein the wordlines and conductive isolation lines comprise a same composition as one another.
5. The memory array of claim 1 wherein the wordlines and conductive isolation lines comprise different compositions relative to one another.
6. The memory array of claim 5 wherein the wordlines comprise metal and the conductive isolation lines consist of conductively-doped silicon.
7. The memory array of claim 1 wherein the second source/drain regions are heavily-doped regions that extend vertically across the wordlines.
8. The memory array of claim 1 wherein the second source/drain regions are heavily-doped regions that extend vertically across the wordlines, and that extend vertically downward beyond uppermost surfaces of the conductive isolation lines.
9. The memory array of claim 1 wherein the fins have bases along n-type doped semiconductor material, and comprising damage regions formed along an upper surface of the n-type doped semiconductor material between bases of adjacent fins along the rows of fins.
10. The memory array of claim 9 wherein the n-type doped semiconductor material is above and directly against p-type doped semiconductor material.
11. A memory array, comprising:
rows of fins; each fin having a first pedestal, a second pedestal and a trough between the first and second pedestals; a first heavily-doped source/drain region being within the first pedestal, a second heavily-doped source/drain region being within the second pedestal, and a channel region being along the trough between the first and second pedestals;
digit lines electrically coupled with the first source/drain regions;
ferroelectric capacitors electrically coupled with the second source/drain regions;
metal-containing wordlines along the rows of fins and overlapping the channel regions; the second heavily-doped source/drain regions vertically overlapping the metal-containing wordlines, and the first heavily-doped source/drain regions not vertically overlapping the metal-containing wordlines; and
conductive isolation lines under the wordlines along the rows of fins, the conductive isolation lines consisting of conductively-doped semiconductor material.
12. The memory array of claim 11 wherein each row of fins has a first side and a second side; the metal-containing wordlines gating each row from both of the first and second sides.
13. The memory array of claim 12 wherein each of the wordlines comprise a pair of wordline components, with one component of said pair extending along the first side of a row of fins and the other component of said pair extending along the second side of the row of fins; and wherein the wordline components of said pair are a same composition as one another.
14. The memory array of claim 11 wherein the second heavily-doped source/drain regions extend vertically across the metal-containing wordlines.
15. A memory array, comprising:
rows of fins; each fin having a first pedestal, a second pedestal and a trough between the first and second pedestals; a first source/drain region being within the first pedestal, a second source/drain region being within the second pedestal, and a channel region being along the trough between the first and second pedestals; the fins extending upwardly from an n-type doped semiconductor material; gettering regions being along segments of the n-type doped semiconductor material between the fins;
digit lines electrically coupled with the first source/drain regions;
ferroelectric capacitors electrically coupled with the second source/drain regions; and
wordlines along the rows of fins and overlapping the channel regions.
16. The memory array of claim 15 wherein each row of fins has a first side and a second side; the wordlines gating each row from both of the first and second sides.
17. The memory array of claim 15 comprising silicon-containing conductive isolation lines under the wordlines along the rows of fins.
18. The memory array of claim 17 wherein each row of fins has a first side and a second side; the silicon-containing conductive isolation lines shielding each row from both of the first and second sides.