IP Library Granted Patent US 10,257,944
Granted Patent B2
US 10,257,944 · App. 15/378,570 · Granted Apr 9, 2019

Board edge connector

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Quick Facts
Patent No.
US 10,257,944
App. No.
15/378,570
Granted
Apr 9, 2019
Kind
B2
Abstract

Apparatuses and methods for forming serial advanced technology attachment (SATA) board edge connectors with electroplated hard gold contacts. One example method can include forming a tie bar on an inner layer of a printed circuit board (PCB), forming a trace on an outer layer of the PCB, forming a via, wherein the via electrically couples the tie bar to the trace, forming a contact coupled to the trace on the outer layer, and sending an electrical charge from the tie bar through the via and the trace to the contact to electroplate the contact.

Claims (19)

1. A method comprising:

forming a tie bar on an inner layer of a printed circuit board (PCB);

forming a trace on an outer layer of the PCB

forming a via, wherein the via electrically couples the tie bar to the trace;

forming a contact coupled to the trace on the outer layer; and

sending an electrical charge from the tie bar through the via and the trace to the contact to electroplate the contact.

2. The method of claim 1 , wherein the contact is being electroplated with gold.

3. The method of claim 1 , wherein the via is removed after the contact is electroplated.

4. The method of claim 3 , wherein the via is removed by drilling the via.

5. The method of claim 4 , wherein the drilling the via electrically disconnects the tie bar from the contact.

6. A method comprising:

forming a tie bar on an inner layer of a printed circuit board (PCB);

forming a trace on an outer layer of the PCB;

forming a via, wherein the via electrically couples the tie bar to the trace;

forming a contact coupled to the trace on the outer layer;

sending an electrical charge from the tie bar through the via and the trace to the contact to electroplate the contact; and

removing the via.

7. The method of claim 6 , wherein the contact does not have parasitic loading.

8. The method of claim 6 , wherein the trace manufacturing includes etching.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: SMITH, KURT B.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040733/0820 →