Integrated structures and methods of forming vertically-stacked memory cells
View Patent ↗Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.
1. A system comprising:
a memory structure comprising:
a stack of alternating dielectric levels and conductive levels;
an insulative material over the stack;
a select gate material over the insulative material;
an opening extending through the select gate material, through the insulative material, and through the stack of alternating dielectric levels and conductive levels; a first region of the opening within the insulative material being wider along a cross-section than a second region of the opening within the select gate material, and being wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels;
cavities extending into the conductive levels;
charge-blocking material and charge-storage structures within the cavities; and
channel material within the opening and adjacent the insulative material and the select gate material.
2. The system of claim 1 , wherein the memory structure further comprises dielectric material along the charge-storage structures, wherein the channel material is also adjacent the dielectric material.
3. The system of claim 2 , wherein the memory structure further comprises an oxide between the channel material and the select gate material.
4. The system of claim 1 , wherein the charge storage structures comprise charge-trapping material.
5. A system comprising:
a conductive material over a semiconductor substrate;
a first gate material over the conductive material;
a stack of alternating dielectric levels and conductive levels over the first gate material;
an insulative material over the stack;
a second gate material over the insulative material;
an opening extending through the second gate material, through the insulative material, and through the stack of alternating dielectric levels and conductive levels, through the first gate material and to the conductive source material; a first region of the opening within the insulative material being wider along a cross-section than a second region of the opening within the second gate material, and being wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels;
doped semiconductor material within the opening and adjacent the insulative material, the select gate material;
cavities extending into the conductive levels;
charge-blocking material and charge-storage structures within the cavities.
6. The system of claim 5 wherein the first region of the opening is wider than a fourth region of the opening within the first gate material along the cross-section.
7. The system of claim 5 wherein the charge-storage structures comprise floating gate material.
8. The system of claim 5 wherein the charge-storage structures comprise charge-trapping material.
9. The system of claim 8 wherein the charge-trapping material comprises silicon nitride.
10. The system of claim 8 wherein the charge-trapping material comprises metal dots.