Physical unclonable function with NAND memory array
Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.
1. A method for generating a data value using a NAND flash array, the method comprising:
reading a number of memory cells at the NAND flash array using an initial read level to generate a first raw string;
determining that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value;
reading the number of memory cells at the NAND flash array using a second read level to generate a second raw string;
determining that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than the threshold value; and
applying a cryptographic function using the second raw string to generate a first data value.
2. The method of claim 1 , wherein the reading of the number of memory cells at the NAND flash array using the initial read level is responsive to a power-up of the NAND flash array.
3. The method of claim 1 , further comprising:
selecting a candidate second read level that is lower than the initial read level;
reading the number of memory cells at the NAND flash array using the candidate second read level to generate a candidate raw string;
determining that a difference between a number of bits from the candidate raw string having a value of logical zero and a number of bits from the candidate raw string having a value of logical one is greater than the threshold value;
determining that the difference between the number of bits from the candidate raw string having a value of logical zero and a number of bits from the candidate raw string having a value of logical one is closer to the threshold value than the difference between the number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one; and
selecting a subsequent candidate second read level that is lower than the candidate second read level.
4. The method of claim 1 , further comprising:
rereading the number of memory cells at the NAND flash array using the second read level to generate a third raw string;
determining that a difference between a number of bits from the third raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is greater than the threshold value; and
determining that a search for a next read level has failed.
5. The method of claim 4 , wherein determining that the search for the next read level has failed comprises determining that at least a portion of the number of memory cells at the NAND flash array has a cell read level less than zero.
6. The method of claim 4 , further comprising:
erasing a block of the NAND flash array comprising the number of memory cells;
applying a first programming pulse to the number of memory cells;
determining that at least a portion of the number of memory cells of the NAND flash array have a cell read level less than a low read level value; and
applying a second programming pulse to the number of memory cells of the NAND flash array.
7. The method of claim 6 , further comprising:
after applying the second programming pulse to the number of memory cells of the NAND flash array, reading the number of memory cells at the NAND flash array using a third read level to generate a third raw string;
determining that a difference between a number of bits from the third raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is not greater than a threshold value; and
applying a cryptographic function using the third raw string to generate a second data value.
8. The method of claim 7 , further comprising selecting the third read level using a distribution of cell read levels of the number of memory cells of the NAND flash array.
9. A system for generating data values, comprising:
a NAND flash array; and
a memory controller configured to perform operations comprising:
reading a number of memory cells at the NAND flash array using an initial read level to generate a first raw string;
determining that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value;
reading the number of memory cells at the NAND flash array using a second read level to generate a second raw string;
determining that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than the threshold value; and
applying a cryptographic function using the second raw string to generate a first data value.
10. The system of claim 9 , wherein the reading of the number of memory cells at the NAND flash array using the initial read level is responsive to a power-up of the NAND flash array.
11. The system of claim 9 , the operations further comprising:
selecting a candidate second read level that is lower than the initial read level;
reading the number of memory cells at the NAND flash array using the candidate second read level to generate a candidate raw string;
determining that a difference between a number of bits from the candidate raw string having a value of logical zero and a number of bits from the candidate raw string having a value of logical one is greater than the threshold value;
determining that the difference between the number of bits from the candidate raw string having a value of logical zero and a number of bits from the candidate raw string having a value of logical one is closer to the threshold value than the difference between the number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one; and
selecting a subsequent candidate second read level that his lower than the candidate second read level.
12. The system of claim 9 , the operations further comprising:
rereading the number of memory cells at the NAND flash array using the second read level to generate a third raw string;
determining that a difference between a number of bits from the third raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is greater than the threshold value; and
determining that a search for a next read level has failed.
13. The system of claim 12 , wherein determining that the search for the next read level has failed comprises determining that at least a portion of the number of memory cells at the NAND flash array has a cell read level less than zero.
14. The system of claim 12 , the operations further comprising:
erasing a block of the NAND flash array comprising the number of memory cells;
applying a first programming pulse to the number of memory cells;
determining that at least a portion of the number of memory cells of the NAND flash array have a cell read level less than a low read level value; and
applying a second programming pulse to the number of memory cells of the NAND flash array.
15. The system of claim 14 , the operations further comprising:
after applying the second programming pulse to the number of memory cells of the NAND flash array, reading the number of memory cells at the NAND flash array using a third read level to generate a third raw string;
determining that a difference between a number of bits from the third raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is not greater than a threshold value; and
applying a cryptographic function using the third raw string to generate a second data value.
16. The system of claim 15 , the operations further comprising selecting the third read level using a distribution of cell read levels of the number of memory cells of the NAND flash array.
17. A non-transitory computer readable medium having instructions thereon that, when executed by at least one processor, causes the processor to perform operations comprising:
reading a number of memory cells at a NAND flash array using an initial read level to generate a first raw string;
determining that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value;
reading the number of memory cells at the NAND flash array using a second read level to generate a second raw string;
determining that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than the threshold value; and
applying a cryptographic function using the second raw string to generate a first data value.
18. The computer readable medium of claim 17 , wherein the reading of the number of memory cells at the NAND flash array using the initial read level is responsive to a power-up of the NAND flash array.
19. The computer readable medium of claim 17 , the operations further comprising:
selecting a candidate second read level that is lower than the initial read level;
reading the number of memory cells at the NAND flash array using the candidate second read level to generate a candidate raw string;
determining that a difference between a number of bits from the candidate raw string having a value of logical zero and a number of bits from the candidate raw string having a value of logical one is greater than the threshold value;
determining that the difference between the number of bits from the candidate raw string having a value of logical zero and a number of bits from the candidate raw string having a value of logical one is closer to the threshold value than the difference between the number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one; and
selecting a subsequent candidate second read level that his lower than the candidate second read level.
20. The computer readable medium of claim 17 , the operations further comprising:
rereading the number of memory cells at the NAND flash array using the second read level to generate a third raw string;
determining that a difference between a number of bits from the third raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is greater than the threshold value; and
determining that a search for a next read level has failed.