Apparatuses and methods for arranging through-silicon vias and pads in a semiconductor device
A semiconductor device may include a bond pad/probe pad pair that includes a bond pad and a probe pad positioned to be adjacent to each other to form an L shape. The device may also include a through-silicon via (TSV) pad positioned to be at least partially or entirely inside the recess area of the L shape. The bond pad and the probe pad may each have an opening, and at least a portion of the opening of the bond pad may extend into a portion of the opening of the probe pad. The arrangement of the bond pad, the probe pad and the TSV may be implemented in a wafer-on-wafer (WOW) that includes multiple stacked wafers. A method of fabricating the TSV may include etching the stacked wafers to form a TSV opening that extends through the multiple wafers, and filling the TSV opening with conductive material.
1. A semiconductor device comprising:
a first bond pad and a first probe pad sharing a same metal layer and each having a respective opening, the first bond pad and the first probe pad adjoining each other to form a first bond pad/probe pad pair, the first bond pad/probe pair defining a first L shape; and
a first through-silicon via (TSV) pad positioned to be at least partially inside a recess area defined at least in part by an inner angle of the first L shape,
wherein the opening of the first bond pad and the opening of the first probe pad meet at a shared boundary in between.
2. The semiconductor device of claim 1 , wherein:
the first bond pad and the first probe pad each have an opening; and
at least a portion of the opening of the first bond pad transitions continuously into a portion of the opening of the first probe pad.
3. The semiconductor device of claim 2 further comprising an upper metal layer, wherein the upper metal layer:
covers and extends beyond the opening of the first bond pad; and
covers and extends beyond the opening of the first probe pad.
4. The semiconductor device of claim 3 , wherein the the first bond pad and the first probe pad share a same passivation layer.
5. The semiconductor device of claim 1 , where a side of the first bond pad and a side of the first probe pad are overlapped at least partially, and wherein a dimension of the overlapped side of the first bond pad is smaller than a dimension of the overlapped side of the first probe pad.
6. The semiconductor device of claim 5 , where the first TSV pad is entirely inside the recess area of the first L shape.
7. The semiconductor device of claim 2 , wherein:
a first bond pad and the first probe pad are positioned to form an additional L shape; and
the opening of the first bond pad and the opening of the first probe pad from a T shape.
8. The semiconductor device of claim 1 further comprising
a second bond pad and a second probe pad positioned to be adjacent toe ach other to form a second bond pad/probe pad pair, the second bond pad/probe pair defining a second L shape; and
a second TSV pad positioned to be at least partially inside a recess area defined at least in part by an inner angle of the second L shape;
wherein the recess area defined by the inner angel of the first L shape and the recess area defined by the inner angle of the second L shape form a joint recess area in which the first TSV pad and the second TSV pad are placed.
9. The semiconductor device of claim 8 , wherein the first bond pad/probe pad pair and the second bond pad/probe pair are positioned at a distance from each other.
10. The semiconductor device of claim 9 , wherein:
the first bond pad and the first probe pad each have an opening;
the second bond pad and the second probe pad each have an opening; and
at least:
at least a portion of the opening of the first bond pad transitions continuously into a portion of the opening of the first probe pad; or
at least a portion of the opening of the second bond pad transitions continuously into a portion of the opening of the second probe pad.
11. A semiconductor device comprising:
a wafer-on-wafer (WOW) chip comprising a plurality of stacked wafers disposed on a base wafer;
at least bond pad and a probe pad disposed on a top of the plurality of stacked wafers, wherein the bond pad and the probe pad share a same metal layer and each have a respective opening, the first bond pad and the first probe pad adjoining each other to forma bond pad/probe pad pair, the bond pad/probe pair defining an L shape; and
a through-silicon via (TSV) positioned to be at least partially inside a recess area defined by an inner angle of the L shape;
wherein the opening of the first bond pad and the opening of the first probe pad meet at is shared boundary in between.
12. The semiconductor device of claim 11 , wherein:
the bond pad and the probe pad each have an opening; and
the opening of the bond pad and the opening of the probe pad are formed together.
13. The semiconductor device of claim 11 , wherein:
each of the plurality of stacked wafers comprises a pad metal having an opening; and
the TSV extends through the plurality of stacked wafers, wherein a width of an opening of the TSV is limited by sizes of the openings of the pad metal in the plurality of stacked wafers.
14. The semiconductor device of claim 13 , wherein:
the sizes of the openings of the pad metal in the plurality of stacked wafers decrease from the top to a bottom of the plurality of stacked wafers; and
the TSV extending through the plurality of stacked wafers form a funnel shape with an opening at a top of the funnel shape wider than an opening at a bottom of the funnel shape.