Methods of synchronizing memory operations and memory systems employing the same

1. A memory system, comprising:

a first memory device having a first latency corresponding to a first command;

a second memory device having a second latency corresponding to a second command,

wherein the second latency differs from the first latency by a latency difference; and

a host operably coupled to the first and second memory devices, and configured to:

send the first command to the first memory device at a first time, and

send the second command to the second memory device at a second time,

wherein the first time and the second time are separated by a delay corresponding to the latency difference,

wherein in response to the first command, the first memory device performs a first operation at a third time, and

wherein in response to the second command, the second memory device performs a second operation at the third time.

2. The memory system of claim 1 , wherein the third time differs from the first time by the first latency, and from the second time by the second latency.

3. The memory system of claim 1 , wherein the host is further configured to:

poll the first and second memory devices to determine the first and second latencies.

4. The memory system of claim 1 , wherein at least one of the first command and the second command is a termination command configured to place one of the first memory device and the second memory device into a termination mode.

5. The memory system of claim 1 , wherein at least one of the first command and the second command is a data transfer command configured to place one of the first memory device and the second memory device into a data transfer mode.

6. The memory system of claim 1 , wherein the first and second memory devices each comprise one of a DIMM module and an NVDIMM module.

7. The memory system of claim 1 , wherein the first and second memory devices are operably coupled to a shared memory bus.

8. A method of operating a memory system including a first memory device having a first latency corresponding to a first command and a second memory device having a second latency corresponding to a second command, wherein the first latency differs from the second latency by a latency difference, the method comprising:

sending a first command to the first memory device at a first time;

sending a second command to the second memory device at a second time, wherein the first time and the second time are separated by a delay corresponding to the latency difference;

the first memory device performing a first operation corresponding to the first command at a third time; and

the second memory device performing a second operation corresponding to the second command at the third time.

9. The method of claim 8 , wherein the third time differs from the first time by the first latency, and from the second time by the second latency.

10. The method of claim 8 , further comprising:

polling the first and second memory devices to determine the first and second latencies.

11. The method of claim 8 , wherein at least one of the first command and the second command is a termination command configured to place one of the first memory device and the second memory device into a termination mode.

12. The method of claim 8 , wherein at least one of the first command and the second command is a data transfer command configured to place one of the first memory device and the second memory device into a data transfer mode.

13. The method of claim 8 , wherein the first and second memory devices each comprise one of a DIMM module and an NVDIMM module.

14. The method of claim 8 , wherein the first and second memory devices are operably coupled to a shared memory bus.