Methods of synchronizing memory operations and memory systems employing the same
View Patent ↗A memory system is provided. The memory system includes a first memory device having a first latency corresponding to a first command and a second memory device having a second latency corresponding to a second command. The second latency differs from the first latency by a latency difference. The memory system further includes a host operably coupled to the first and second memory devices. The host is configured to send the first command to the first memory device at a first time, and to send the second command to the second memory device at a second time. The first time and the second time are separated by a delay corresponding to the latency difference.
1. A memory system, comprising:
a first memory device having a first latency corresponding to a first command;
a second memory device having a second latency corresponding to a second command, wherein the second latency differs from the first latency by a latency difference; and
a host operably coupled to the first and second memory devices, and configured to:
send the first command to the first memory device at a first time, and
send the second command to the second memory device at a second time,
wherein the first time and the second time are separated by a delay corresponding to the latency difference,
wherein the first command is a termination command configured to place the first memory device into a termination mode, and the second command is a data transfer command place the second memory device into a data transfer mode.
2. The memory system of claim 1 , wherein:
in response to the first command, the first memory device performs a first operation at a third time, and
in response to the second command, the second memory device performs a second operation at the third time.
3. The memory system of claim 2 , wherein the third time differs from the first time by the first latency, and from the second time by the second latency.
4. The memory system of claim 1 , wherein the host is further configured to:
poll the first and second memory devices to determine the first and second latencies.
5. The memory system of claim 1 , wherein the first and second memory devices each comprise one of a DIMM module and an NVDIMM module.
6. The memory system of claim 1 , wherein the first and second memory devices are operably coupled to a shared memory bus.
7. A memory system, comprising:
a first memory device having a first latency corresponding to a termination command;
a second memory device having a second latency corresponding to a data transfer command, wherein the second latency differs from the first latency by a latency difference; and
a host operably coupled to the first and second memory devices, and configured to:
send the termination command to the first memory device at a first time, and
send the data transfer command to the second memory device at a second time,
wherein the first time and the second time are separated by a delay corresponding to the latency difference.
8. The memory system of claim 7 , wherein:
in response to the termination command, the first memory device enters a termination mode at a third time, and
in response to the data transfer command, the second memory device performs a data transfer operation at the third time.
9. The memory system of claim 8 , wherein the third time differs from the first time by the first latency, and from the second time by the second latency.
10. The memory system of claim 7 , wherein the host is further configured to:
poll the first and second memory devices to determine the first and second latencies.
11. The memory system of claim 7 , wherein the data transfer command is one of a read command, a write command, or a status command.
12. The memory system of claim 7 , wherein the first and second memory devices each comprise one of a DIMM module and an NVDIMM module.
13. The memory system of claim 7 , wherein the first and second memory devices are operably coupled to a shared memory bus.
14. A method of operating a memory system including a first memory device having a first latency corresponding to a first command and a second memory device having a second latency corresponding to a second command, wherein the first latency differs from the second latency by a latency difference, the method comprising:
sending a first command to the first memory device at a first time;
sending a second command to the second memory device at a second time, wherein the first time and the second time are separated by a delay corresponding to the latency difference,
wherein the first command is a termination command configured to place the first memory device into a termination mode, and the second command is a data transfer command place the second memory device into a data transfer mode.
15. The method of claim 14 , further comprising:
the first memory device performing a first operation corresponding to the first command at a third time; and
the second memory device performing a second operation corresponding to the second command at the third time.
16. The method of claim 15 , wherein the third time differs from the first time by the first latency, and from the second time by the second latency.
17. The method of claim 14 , further comprising:
polling the first and second memory devices to determine the first and second latencies.
18. The method of claim 14 , wherein the first and second memory devices each comprise one of a DIMM module and an NVDIMM module.
19. The method of claim 14 , wherein the first and second memory devices are operably coupled to a shared memory bus.