IP Library Granted Patent US 10,833,630
Granted Patent B2
US 10,833,630 · App. 16/225,678 · Granted Nov 10, 2020

Apparatuses and methods for temperature independent oscillators

Inventors: Jun Wu (Jiangsu, CN); Dong Pan (Boise, ID)
Assignee: Micron Technology, Inc.
H03B5/04G11C7/1075G11C11/40611G11C11/40615H03B5/24H03K3/011H03K3/0231H03K3/03H03K4/502H03L1/026
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Quick Facts
Patent No.
US 10,833,630
App. No.
16/225,678
Granted
Nov 10, 2020
Kind
B2
Abstract

Apparatuses and methods for temperature independent oscillator circuits are disclosed herein. An example apparatus may include a pulse generator circuit configured to provide a periodic pulse based on the charging and discharging and discharging of a capacitor and further based on a reference voltage. The pulse generator circuit may include a capacitor coupled between a first reference voltage and a first node, wherein the capacitor is configured to be charged and discharged through the node in response to the periodic pulse, a resistor and a diode coupled in series between a second node and a second reference voltage, and a comparator coupled to the first and second nodes and configured to provide the periodic pulse based on voltages on the first and second nodes, wherein a period of the periodic pulse is based at least on the resistor and the a current.

Claims (45)

1. An apparatus; comprising:

a pulse generator circuit configured to provide a periodic pulse based on charging and discharging of a capacitor, the pulse generator circuit comprising:

the capacitor coupled to a first node, wherein the capacitor is configured to be charged and discharged through the first node in response to the periodic pulse;

a resistor and a diode coupled to a second node;

a comparator coupled to the first and second nodes and configured to provide the periodic pulse based at least on the resistor and a current;

a first transistor coupled to the first node; and

a second transistor coupled to the first node and a third reference voltage, and wherein the first and second transistors are configured to be enabled and disabled in response to the periodic pulse.

2. The apparatus of claim 1 , wherein a voltage of the first node is time-varying and a voltage of the second node is constant.

3. The apparatus of claim 1 , further comprising:

a flip-flop coupled to an output of the comparator.

4. The apparatus of claim 3 , wherein the flip-flop is configured to provide an oscillating signal in response to the periodic pulse, and

wherein a period of the oscillating signal is based on a period of the periodic pulse.

5. The apparatus of claim 1 , wherein the pulse generator circuit is further configured to provide the periodic pulse based on first and second reference voltages, and

wherein the resistor and the diode are coupled in series between the second node and the second reference voltage.

6. The apparatus of claim 1 , wherein the pulse generator circuit further comprises another resistor coupled to the second node, and a third transistor coupled to the other resistor.

7. The apparatus of claim 1 , wherein the pulse generator circuit further comprises a current source configured to provide the current, and

wherein the second node has a voltage based on the current, the resistor and a junction voltage of the diode.

8. The apparatus of claim 1 , wherein the resistor, the diode, and the current of the pulse generator circuit have respective temperature coefficients that cancel each other out.

9. An apparatus, comprising:

a refresh timing circuit configured to provide refresh commands based on a number of periods of an oscillator signal; and

an oscillator circuit comprising:

a flip-flop configured to provide the oscillator signal; and

a pulse generator circuit coupled to the flip-flop, the pulse generator circuit comprising:

first and second transistors;

a series-coupled resistor and diode; and

a comparator having a first input coupled to the first and second transistors, a second input coupled to the series-coupled resistor and diode, and an output coupled to the flip-flop, wherein the first transistor is further coupled to a first node, and the first transistor includes a Gate coupled to an output of the comparator.

10. The apparatus of claim 9 , wherein the oscillator circuit further comprises a second transistor coupled between the first node and a reference voltage, and the second transistor includes a gate coupled to the output of the comparator.

11. The apparatus of claim 10 , wherein the pulse generator circuit is configured to provide a periodic pulse signal, and

wherein the oscillator circuit further comprises a capacitor coupled between the first node and another reference voltage, and the capacitor is configured to be charged and discharged responsive to the periodic pulse signal.

12. The apparatus of claim 9 , wherein the oscillator circuit further comprises a current source configured to provide a constant current, and wherein the

second transistor is further coupled between the first node and a reference voltage.

13. The apparatus of claim 12 , wherein the oscillator circuit further comprises a capacitor configured to be charged by the constant current when the first transistor is enabled and the second transistor is disabled, and

wherein the capacitor is further configured to be discharged when the first transistor is disabled and the second transistor is enabled.

14. An apparatus, comprising:

a refresh timing circuit configured to provide refresh commands based on a number of periods of an oscillator signal; and

an oscillator circuit comprising:

a pulse generator circuit configured to provide a periodic pulse signal, the pulse generator circuit comprising:

a comparator having first and second inputs coupled to first and second nodes, respectively;

first and second transistors coupled to the first input, wherein the first transistor comprises a gate coupled to an output of the comparator; and

a series-coupled resistor and diode,

wherein the series-coupled resistor and diode is coupled to the second node.

15. The apparatus of claim 14 , wherein the oscillator circuit further comprises a flip-flop coupled to the output of the comparator, and the oscillator circuit is configured to provide the oscillator signal.

16. The apparatus of claim 14 , wherein the pulse generator circuit further comprises a capacitor coupled to the first node.

17. The apparatus of claim 16 , wherein the capacitor is configured to be charged when the first transistor is enabled and the second transistor is disabled, and

wherein the capacitor is configured to be discharged when the first transistor is disabled and the second transistor is enabled.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2018
From: WU, JUN; PAN, DONG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047818/0164 →