IP Library Granted Patent US 10,651,375
Granted Patent B2
US 10,651,375 · App. 16/160,518 · Granted May 12, 2020

Memory cells, semiconductor devices including the memory cells, and methods of operation

Inventors: Timothy A. Quick (Boise, ID); Eugene P. Marsh (El Granada, CA); Stefan Uhlenbrock (Boise, ID); Chet E. Carter (Boise, ID); Scott E. Sills (Boise, ID)
Assignee: Micron Technology, Inc.
H01L45/085H01L45/1233H01L45/141H01L45/1608H01L45/1616
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,651,375
App. No.
16/160,518
Granted
May 12, 2020
Kind
B2
Abstract

Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. Also disclosed are fabrication methods and semiconductor devices including the disclosed memory cells.

Claims (29)

1. A memory cell, comprising:

an ion-source material adjacent a cell material; and

a discontinuous interfacial material between the cell material and the ion-source material, the discontinuous interfacial material comprising atoms adherent to the cell material and adjacent atoms of the discontinuous interfacial material spaced by a distance greater than or equal to a diameter of ions of the ion-source material.

2. The memory cell of claim 1 , wherein the discontinuous interfacial material comprises metal atoms.

3. The memory cell of claim 1 , wherein the atoms adherent to the cell material comprise atoms chemisorbed to the cell material.

4. The memory cell of claim 1 , wherein the atoms adherent to the cell material comprise a centralized atom and one or more ligands bonded to the centralized atom.

5. The memory cell of claim 1 , wherein the atoms adherent to the cell material are bonded to at least one atom from the ion-source material.

6. The memory cell of claim 5 , wherein the atoms adherent to the cell material are bonded to another atom bonded to the ion-source material.

7. The memory cell of claim 1 , wherein the cell material comprises a material permeable to atoms of the ion-source material.

8. The memory cell of claim 1 , wherein the cell material comprises a semiconductive chalcogenide solid-electrolyte.

9. A semiconductor device, comprising:

memory cells, at least one memory cell of the memory cells comprising:

an ion-source material over a cell material; and

a discontinuous interfacial material between the cell material and the ion-source material, the discontinuous interfacial material comprising interfacial complexes spaced apart by a distance greater than or equal to a diameter of ions of the ion-source material and the interfacial complexes comprising a partial monolayer of the discontinuous interfacial material.

10. The semiconductor device of claim 9 , further comprising a first electrode and a second electrode in operative communication with the cell material and the ion-source material.

11. The semiconductor device of claim 10 , wherein the first electrode comprises a single material.

12. The semiconductor device of claim 10 , wherein the first electrode comprises more than one material.

13. The semiconductor device of claim 10 , wherein metal atoms of the ion-source material electroconductively connect the first electrode and the second electrode.

14. The semiconductor device of claim 10 , wherein metal atoms of the ion-source material electroconductively connect the first electrode and the ion-source material.

15. The semiconductor device of claim 9 , wherein the ion-source material comprises a copper-containing material or a silver-containing material.

16. A method of operating a semiconductor device comprising:

applying a voltage to a semiconductor device comprising memory cells, at least one of the memory cells comprising an ion-source material over a cell material; and

diffusing ions from the ion-source material through a discontinuous interfacial material between the cell material and the ion-source material to form at least one conductive path between a first electrode and the ion-source material, the discontinuous interfacial material comprising atoms adherent to the cell material, adjacent atoms of the discontinuous interfacial material spaced by a distance greater than or equal to a diameter of the ions of the ion-source material, and the discontinuous interfacial material comprising a thickness of only one adherent atom.

17. The method of claim 16 , wherein diffusing ions from the ion-source material through a discontinuous interfacial material comprises diffusing at least one of copper ions or silver ions through the discontinuous interfacial material.

18. The method of claim 16 , wherein diffusing ions from the ion-source material through a discontinuous interfacial material between the cell material and the ion-source material comprises forming the at least one conductive path electroconductively connecting the first electrode and the ion-source material of the semiconductor device.

19. The method of claim 16 , wherein diffusing ions from the ion-source material through a discontinuous interfacial material between the cell material and the ion-source material comprises forming the at least one conductive path electroconductively connecting the first electrode and a second electrode.

20. The method of claim 16 , wherein forming at least one conductive path comprises switching a memory state of the memory cells from a high resistance state to a low resistance state.

21. The semiconductor device of claim 16 , wherein forming at least one conductive path comprises forming a filament extending through the discontinuous interfacial material.

22. The method of claim 16 , further comprising reversing a polarity of the voltage to dissipate the at least one conductive path.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →