IP Library Granted Patent US 10,529,430
Granted Patent B2
US 10,529,430 · App. 16/180,154 · Granted Jan 7, 2020

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

Inventors: Kenneth J. Eldredge (Boise, ID); Frankie F. Roohparvar (Monte Sereno, CA); Luca De Santis (Avezzano, IT); Tommaso Vali (Sezze, IT)
Assignee: Micron Technology, Inc.
G11C16/28G11C15/00G11C15/046G11C16/0483
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Quick Facts
Patent No.
US 10,529,430
App. No.
16/180,154
Granted
Jan 7, 2020
Kind
B2
Abstract

Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.

Claims (31)

1. A method of operating a memory device, comprising:

comparing input data to data stored in memory cells coupled to a data line;

comparing a representation of a level of current in the data line to a reference;

determining that the input data potentially matches the data stored in the memory cells in response to the representation of the level of current in the data line being less than or equal to the reference; and

determining that the input data does not match the data stored in the memory cells in response to the representation of the level of current in the data line being greater than the reference;

wherein comparing a representation of a level of current in the data line to a reference comprises comparing the representation of the level of current in the data line to a reference that compensates for current leakage through a memory cell coupled to the data line that is turned off.

2. A method of operating a memory device, comprising:

comparing input data to data stored in memory cells coupled to a data line;

comparing a representation of a level of current in the data line to a reference;

deeming the input data to match the data stored in the memory cells in response to the representation of the level of current in the data line being less than the reference; and

deeming the input data to not match the data stored in the memory cells in response to the representation of the level of current in the data line being greater than the reference;

wherein comparing a representation of a level of current in the data line to a reference comprises comparing the representation of the level of current in the data line to a reference that compensates for current leakage through a memory cell coupled to the data line that is turned off.

3. A method of operating a memory device, comprising:

comparing input data to data stored in memory cells coupled to a data line;

comparing a representation of a level of current in the data line to a reference;

deeming the input data to match the data stored in the memory cells in response to the representation of the level of current in the data line being less than the reference; and

deeming the input data to not match the data stored in the memory cells in response to the representation of the level of current in the data line being greater than the reference; and

deeming the input data to match the data stored in the memory cells in response to the representation of the level of current in the data line being equal to the reference.

4. A method of operating a memory device, comprising:

comparing input data to stored data, wherein each digit of stored data is stored in a respective pair of memory cells of a respective string of series-connected memory cells of a plurality of strings of series-connected memory cells coupled to a data line, wherein each digit of the input data corresponds to a respective digit of the stored data, and wherein comparing the input data to the stored data comprises comparing a particular digit of the input data to its respective digit of the stored data by applying a pair of voltages representative of a value of the particular digit of the input data to control gates of the respective pair of memory cells of its respective string of series-connected memory cells;

causing different levels of current to respectively flow through different strings of series-connected memory cells of the plurality of strings of series-connected memory cells from the data line when different digits of the input data respectively mismatch their respective digits of the stored data;

comparing a representation of a level of current in the data line to a reference;

deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than or equal to the reference; and

deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference;

wherein causing the causing different levels of current to respectively flow through the different strings of series-connected memory cells comprises causing a first level of current to flow through a first string of series-connected memory cells of the plurality of strings of series-connected memory cells and causing a second level of current to flow through a second string of series-connected memory cells of the plurality of strings of series-connected memory cells, wherein the first level of current is a factor of two greater than the second level of current.

5. A method of operating a memory device, comprising:

comparing input data to stored data, wherein each digit of stored data is stored in a respective pair of memory cells of a respective string of series-connected memory cells of a plurality of strings of series-connected memory cells coupled to a data line, wherein each digit of the input data corresponds to a respective digit of the stored data, and wherein comparing the input data to the stored data comprises comparing a particular digit of the input data to its respective digit of the stored data by applying a pair of voltages representative of a value of the particular digit of the input data to control gates of the respective pair of memory cells of its respective string of series-connected memory cells;

comparing a representation of a level of current in the data line to a reference;

deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than or equal to the reference; and

deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference;

wherein deeming the input data to match the stored data comprises deeming the input data to match the stored data when less than all digits of the input data match their respective digit of the stored data.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →
Continuity (5)
Continuation 15645009 · Jul 10, 2017
Continuation 14798845 · Jul 14, 2015
Division 13864659 · Apr 17, 2013
Provisional Application 61625286 · Apr 17, 2012
Related Publication 20190074069A1 · Mar 7, 2019