IP Library Granted Patent US 10,580,687
Granted Patent B2
US 10,580,687 · App. 16/183,450 · Granted Mar 3, 2020

Methods of forming one or more covered voids in a semiconductor substrate

Inventor: David H. Wells (Boise, ID)
Assignee: Micron Technology, Inc.
H01L21/764H01L21/0265H01L21/02381H01L21/02488H01L21/02532H01L21/02639H01L21/2015
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Quick Facts
Patent No.
US 10,580,687
App. No.
16/183,450
Granted
Mar 3, 2020
Kind
B2
Abstract

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Claims (11)

1. Integrated circuitry comprising:

a semiconductor-on-insulator substrate having a mean outermost global surface; the substrate comprising monocrystalline silicon-containing material, an insulator over the monocrystalline silicon-containing material, and an elemental-form silicon-comprising material over the insulator;

a plurality of elongated cooling conduits running generally parallel the mean outermost global surface within the insulator, the conduits having opposing sidewalls that comprise the insulator that is over the monocrystalline silicon-containing material; and

cooling fluid within the cooling conduits.

2. The integrated circuitry of claim 1 wherein the cooling conduits have ceilings comprising the elemental-form silicon-comprising material.

3. The integrated circuitry of claim 1 wherein the insulator comprises silicon dioxide.

4. The integrated circuitry of claim 1 wherein the insulator comprises silicon nitride.

5. The integrated circuitry of claim 1 wherein the insulator comprises silicon dioxide and silicon nitride.

6. The integrated circuitry of claim 1 wherein the cooling fluid comprises liquid.

7. The integrated circuitry of claim 1 wherein the cooling fluid comprises gas.

8. The integrated circuitry of claim 1 wherein the cooling fluid comprises liquid and gas.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →