Multiple endianness compatibility

1. A method, comprising:

receiving a plurality of bytes in a little-endian bytewise, big-endian bitwise format such that the plurality of bytes are in a sequential format and the bits in each byte of the plurality of bytes are in a non-bit-sequential format; and

reordering, using reordering circuitry comprising multiplexers, the bits in each byte of the plurality of bytes on a bytewise basis, without regard to a number of the bytes of the plurality of bytes and as each byte is received from a processor, such that the bits in each byte of the plurality of bytes are arranged in a bit-sequential format.

2. The method of claim 1 , wherein the bit-sequential format is a bit-sequential little endian format where the bits are arranged from a least significant bit of each byte of the plurality of bytes being stored in a most significant position and a most significant bit of each byte of the plurality of bytes being stored in a least significant position.

3. The method of claim 1 , wherein the plurality of bytes are received at a memory device.

4. The method of claim 1 , wherein the plurality of bytes stored in the memory cells are stored in memory cells coupled to a same access line of the array.

5. The method of claim 1 , further comprising:

storing each of the bits in one of a respective number of compute components; and

shifting each of the bits from a compute component coupled to a memory cell storing a lesser significant bit to a compute component coupled to a memory cell storing a more significant bit.

6. The method of claim 1 , further comprising:

storing each of the bits in one of a respective number of compute components; and

shifting each of the bits from a compute component coupled to a memory cell storing a more significant bit to a compute component coupled to a memory cell storing a lesser significant bit.

7. The method of claim 1 , comprising reordering the bits from a bit-sequential little endian format to a non-bit-sequential little endian format on a byte-by-byte basis after shifting the bits.

8. The method of claim 7 , comprising sending the reordered bits to a processing resource.

9. The method of claim 1 , wherein reordering the bits in each byte comprises reordering a most significant bit of a first byte from a most significant bit position to a least significant bit position.

10. The method of claim 9 , wherein reordering the bits in each byte comprises-reordering a least significant bit of the first byte from a least significant bit position to the most significant bit position.

11. A method, comprising:

receiving, at reordering circuitry, a plurality of bytes in a bytewise little endian bitwise big endian format such that the plurality of bytes are in a sequential format and the bits in each byte of the plurality of bytes are in a non-bit-sequential format, wherein the reordering circuitry comprises an engine within a controller of a memory device; and

using the reordering circuitry to reorder the plurality of bytes on a bytewise basis, without regard to a number of the bytes of the plurality of bytes and as each byte is received from a processor, into a bit-sequential little endian format.

12. The method of claim 11 , further comprising using the reordering circuitry to reverse an order of the bits of the plurality of bytes stored in the group of memory cells in the bit-sequential little endian format, such that the plurality of bytes are in the bytewise little endian bitwise big endian format.

13. The method of claim 12 , further comprising providing the plurality of bytes in the bytewise little endian bitwise big endian format.

14. The method of claim 11 , wherein a first bit position in the order of bits in each of a plurality of bytes is a most significant bit position and an eighth bit position in the order is a least significant bit position.

15. The method of claim 11 , wherein the bits are ordered in the bit-sequential little endian format, prior to the reversing, such that a most significant bit of a first byte of the plurality of bytes is in a least significant bit position of the first byte.

16. The method of claim 15 , wherein the bits are ordered in the bit-sequential little endian format, prior to the reversing, such that a least significant bit of the first byte is in a most significant bit position of the first byte.

17. The method of claim 16 , wherein the reversed bits are ordered in the bytewise little endian format such that:

a most significant bit of the first byte is in a most significant bit position of the first byte; and

a least significant bit of the first byte is in a least significant bit position of the first byte.

18. A system comprising:

a host configured to send bits of a plurality of bytes in a bytewise little endian, bitwise big endian format such that the corresponding bits in each byte are in a non-sequential format;

a memory device comprising reordering circuitry, wherein the memory device is configured to receive the bits of the plurality of bytes and reorder the bits to a bytewise little endian, bitwise little endian format, without regard to a number of the bytes of the plurality of bytes and as each byte is received by the memory device, using multiplexers of the reordering circuitry;

wherein the corresponding reordered bits in each byte are in a sequential format on a bytewise basis and without regard to a number of bytes of the plurality of bytes.

19. The system of claim 18 , wherein the memory device further comprises reordering circuitry,

wherein the reordering circuitry is configured to reverse an order of the bits of the plurality of bytes in the bytewise little endian, bitwise little endian format stored in a group of memory cells of the memory array, such that the plurality of bytes are in the bytewise little endian, bitwise big endian format.

20. The system of claim 18 , wherein the memory device is further configured to:

reorder the reordered bits back to the bytewise little endian, bitwise big endian format; and

send the re-reordered bits to the host.