IP Library Granted Patent US 11,329,062
Granted Patent B2
US 11,329,062 · App. 16/230,382 · Granted May 10, 2022

Memory arrays and methods used in forming a memory array

Inventors: Justin B. Dorhout (Boise, ID); Erik Byers (Boise, ID); Merri L. Carlson (Boise, ID); Indra V. Chary (Boise, ID); Damir Fazil (Boise, ID); John D. Hopkins (Meridian, ID); Nancy M. Lomeli (Boise, ID); Eldon Nelson (Dripping Springs, TX); Joel D. Peterson (Boise, ID); Dimitrios Pavlopoulos (Glendale, CA); Paolo Tessariol (Arcore, IT); Lifang Xu (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/11582H01L21/76802H01L27/1157H01L29/66833H01L29/7926
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Quick Facts
Patent No.
US 11,329,062
App. No.
16/230,382
Granted
May 10, 2022
Kind
B2
Abstract

A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an insulator tier above the wordline tiers. The insulator tier comprises first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus. The first insulator material is patterned to form first horizontally-elongated trenches in the insulator tier. Second insulator material is formed in the first trenches along sidewalls of the first insulator material. The second insulator material is of different composition from that of the first insulator material and narrows the first trenches. After forming the second insulator material, second horizontally-elongated trenches are formed through the insulative tiers and the wordline tiers. The second trenches are horizontally along the narrowed first trenches laterally between and below the second insulator material. Elevationally-extending strings of memory cells are formed in the stack. Structure independent of method is disclosed.

Claims (68)

1. A method used in forming a memory array, comprising:

forming a stack comprising vertically-alternating insulative tiers and wordline tiers, the stack comprising a horizontally-elongated insulator-material line that extends vertically through an uppermost of the insulative tiers and an uppermost of the wordline tiers;

forming an insulator tier above the wordline tiers and above the horizontally-elongated insulator-material line; the insulator tier comprising a first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus;

patterning the first insulator material to form first horizontally-elongated trenches in the insulator tier and to form horizontally-elongated first-insulator-material lines that individually have a longitudinal outline shape of individual wordlines to be formed in individual of the wordline tiers;

forming horizontally-elongated lines of a second insulator material in the first trenches along sidewalls of the first-insulator-material lines, the second insulator material being of a different composition from that of the first insulator material and narrowing the first trenches, the second-insulator-material lines having individual bases that are above the uppermost of the wordline tiers;

after forming the second-insulator-material lines, forming second horizontally-elongated trenches through the insulative tiers and the wordline tiers, the second trenches being horizontally along the narrowed first trenches laterally between and below the second-insulator-material lines and forming the wordline tiers to have the longitudinal outline shape of the individual wordlines in the individual wordline tiers;

forming elevationally-extending strings of memory cells in the stack;

forming a channel material vertically through the horizontally-elongated insulator-material line.

2. The method of claim 1 wherein said one or more of carbon, oxygen, boron, and phosphorus in the first insulator material has a total concentration of at least about 2 atomic percent.

3. The method of claim 2 wherein said total concentration is no more than about 20 atomic percent.

4. The method of claim 2 wherein said one or more of carbon, oxygen, boron, and phosphorus in the first insulator material has a total concentration of at least about 4 atomic percent.

5. The method of claim 4 wherein said total concentration is at least about 10 atomic percent.

6. The method of claim 1 wherein the one or more comprises carbon.

7. The method of claim 1 wherein the one or more comprises oxygen.

8. The method of claim 1 wherein the one or more comprises boron.

9. The method of claim 1 wherein the one or more comprises phosphorus.

10. The method of claim 1 wherein the one or more comprises only one of carbon, oxygen, boron, and phosphorus.

11. The method of claim 1 wherein the one or more comprises at least two of carbon, oxygen, boron, and phosphorus.

12. The method of claim 1 comprising forming the first trenches to extend through the first insulator material.

13. The method of claim 1 wherein the insulative tiers comprise an insulative material, the first insulator material being of a different composition from that of the insulative material of all of the insulative tiers.

14. The method of claim 1 wherein forming the second insulator material in the first trenches along the sidewalls of the first-insulator-material lines comprises:

forming the second insulator material atop the first insulator material, along sidewalls of the first trenches, and directly above bases of the first trenches; and

maskless anisotropically etching the second insulator material to remove such from being directly above the first-trench bases except where it is immediately adjacent the first-trench sidewalls and to remove such from being atop the first insulator material.

15. The method of claim 1 wherein,

the patterning comprises forming a patterned masking layer atop the stack and using the patterned masking layer as a mask while etching the first insulator material to form the first horizontally-elongated trenches in the insulator tier; and

the insulator tier is formed across a staircase region that is adjacent the memory array and where an electrical contact is made to the wordline tiers, the patterned masking layer being formed atop the insulator tier in the staircase region, and further comprising etching the first insulator material of the insulator tier in the staircase region using the patterned masking layer therein as a mask during the etching of the first insulator material to form the first horizontally-elongated trenches in the insulator tier that is in the memory array.

16. A method used in forming a memory array, comprising:

forming a stack comprising vertically-alternating insulative tiers and wordline tiers, the stack comprising a horizontally-elongated insulator-material line that extends vertically through an uppermost of the insulative tiers and an uppermost of the wordline tiers;

forming an insulator tier above the wordline tiers and above the horizontally-elongated insulator-material line; the insulator tier comprising a first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus;

patterning the first insulator material to form first horizontally-elongated trenches in the insulator tier and to form horizontally-elongated first-insulator-material lines that individually have a longitudinal outline shape of individual wordlines to be formed in individual of the wordline tiers;

forming horizontally-elongated lines of a second insulator material in the first trenches along sidewalls of the first-insulator-material lines, the second insulator material being of a different composition from that of the first insulator material and narrowing the first trenches, the second-insulator-material lines having individual bases that are above the uppermost of the wordline tiers;

after forming the second-insulator-material lines, forming second horizontally-elongated trenches through the insulative tiers and the wordline tiers, the second trenches being horizontally along the narrowed first trenches laterally between and below the second-insulator-material lines and forming the wordline tiers to have the longitudinal outline shape of the individual wordlines in the individual wordline tiers;

forming elevationally-extending strings of memory cells in the stack; and

forming longitudinally-spaced strings of a channel material vertically through the horizontally-elongated insulator-material line.

17. A method used in forming a memory array, comprising:

forming a stack comprising vertically-alternating insulative tiers and wordline tiers, the stack comprising a horizontally-elongated insulator-material line that extends vertically through an uppermost of the insulative tiers and an uppermost of the wordline tiers;

forming an insulator tier above the wordline tiers and above the horizontally-elongated insulator-material line; the insulator tier comprising a first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus;

patterning the first insulator material to form first horizontally-elongated trenches in the insulator tier;

forming a second insulator material in the first trenches along sidewalls of the first insulator material, the second insulator material being of a different composition from that of the first insulator material and narrowing the first trenches;

after forming the second insulator material, forming second horizontally-elongated trenches through the insulative tiers and the wordline tiers, the second trenches being horizontally along the narrowed first trenches laterally between and below the second insulator material;

forming elevationally-extending strings of memory cells in the stack;

forming a sacrificial material in the wordline tiers;

etching the sacrificial material away from the wordline tiers selectively relative to the insulative tiers;

replacing the sacrificial material from the wordline tiers with a conductive material that is used to form individual wordlines in the wordline tiers;

the second insulator material in the first trenches along the sidewalls of the first insulator material shielding the first insulator material from being laterally etched during the etching; and

forming a channel material vertically through the horizontally-elongated insulator-material line.

18. A method used in forming a memory array, comprising:

forming a stack comprising vertically-alternating insulative tiers and wordline tiers, the stack comprising a horizontally-elongated insulator-material line that extends vertically through an uppermost of the insulative tiers and an uppermost of the wordline tiers;

forming an insulator tier above the wordline tiers and above the horizontally-elongated insulator-material line; the insulator tier comprising a first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus;

patterning the first insulator material to form first horizontally-elongated trenches in the insulator tier;

forming a second insulator material in the first trenches along sidewalls of the first insulator material, the second insulator material being of a different composition from that of the first insulator material and narrowing the first trenches;

after forming the second insulator material, forming second horizontally-elongated trenches through the insulative tiers and the wordline tiers, the second trenches being horizontally along the narrowed first trenches laterally between and below the second insulator material;

forming elevationally-extending strings of memory cells in the stack;

forming a sacrificial material in the wordline tiers;

etching the sacrificial material away from the wordline tiers selectively relative to the insulative tiers;

replacing the sacrificial material from the wordline tiers with a conductive material that is used to form individual wordlines in the wordline tiers;

the second insulator material in the first trenches along the sidewalls of the first insulator material shielding the first insulator material from being laterally etched during the etching; and

forming longitudinally-spaced strings of a channel material vertically through the horizontally-elongated insulator-material line.

19. A method used in forming a memory array, comprising:

forming a stack comprising vertically-alternating insulative tiers and wordline tiers, the stack comprising an insulator tier above the wordline tiers;

the insulator tier comprising a first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus;

patterning the first insulator material to form first horizontally-elongated trenches in the insulator tier and to form horizontally-elongated first-insulator-material lines that individually have a longitudinal outline shape of individual wordlines to be formed in individual of the wordline tiers;

forming horizontally-elongated lines of a second insulator material in the first trenches along sidewalls of the first-insulator-material lines, the second insulator material being of a different composition from that of the first insulator material and narrowing the first trenches, the second-insulator-material lines having individual bases that are above an uppermost of the wordline tiers;

after forming the second-insulator-material lines, forming second horizontally-elongated trenches through the insulative tiers and the wordline tiers, the second trenches being horizontally along the narrowed first trenches laterally between and below the second-insulator-material lines and forming the wordline tiers to have the longitudinal outline shape of the individual wordlines in the individual wordline tiers;

forming elevationally-extending strings of memory cells in the stack, the strings of memory cells comprising channel-material strings;

forming individual void spaces that extend vertically through both of the insulator tier and an uppermost of the insulative tiers radially inward of the channel-material strings;

forming a first conductive via in individual of the void spaces radially inward of and directly against the channel material of the channel-material strings, the first conductive via extending vertically through each of the insulator tier and the uppermost insulative tier; and

forming a second conductive via directly against a top surface of individual of the first conductive vias and which are individually radially offset from the first conductive vias and which are directly against the first insulator material.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051026/0568 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050718/0764 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2019
From: DORHOUT, JUSTIN B.; BYERS, ERIK; CARLSON, MERRI L.; CHARY, INDRA V.; FAZIL, DAMIR; HOPKINS, JOHN D.; LOMELI, NANCY M.; NELSON, ELDON; PETERSON, JOEL D.; PAVLOPOULOS, DIMITRIOS; TESSARIOL, PAOLO; XU, LIFANG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 048453/0093 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2019
From: DORHOUT, JUSTIN B.; BYERS, ERIK; CARLSON, MERRI L.; CHARY, INDRA V.; FAZIL, DAMIR; HOPKINS, JOHN D.; LOMELI, NANCY M.; NELSON, ELDON; PETERSON, JOEL D.; TESSARIOL, PAOLO; XU, LIFANG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 048094/0308 →
SUPPLEMENT NO. 11 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048082/0860 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Jan 16, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048082/0889 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2018
From: BYERS, ERIK; CARLSON, MERRI L.; FAZIL, DAMIR; LOMELI, NANCY M.; PETERSON, JOEL D.; TESSARIOL, PAOLO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047845/0385 →