Methods of determining host clock frequency for run time optimization of memory and memory devices employing the same
A memory device is provided. The memory device includes one or more memories and a connector operably coupled to the one or more memories and configured to receive signals including a first reference clock signal from a connected host. The memory device further includes circuitry configured to determine a frequency of the first reference clock signal. The circuitry can be configured to generate a second reference clock signal and to compare the first and second reference clock signals to determine the frequency of the first reference clock signal. The memory devices can further include circuitry configured to adjust one or more operating characteristics of the memory device in response to the determined frequency of the first reference clock signal.
1. A memory device comprising:
one or more memories configured to receive a first reference clock signal from a connected host;
circuitry configured to generate a second reference clock signal;
circuitry configured to compare the first and second reference clock signals to determine the frequency of the first reference clock signal;
circuitry configured to store the determined frequency; and
circuitry configured to adjust one or more voltages of the memory device in response to the stored frequency of the first reference clock signal.
2. The memory device of claim 1 , wherein the circuitry configured to compare the first and second reference clock signals includes:
circuitry configured to count edges of the first reference clock signal over a predetermined number of cycles of the second reference clock signal.
3. The memory device of claim 1 , wherein the one or more memories are DRAM memories.
4. The memory device of claim 1 , wherein the memory device is a dual in-line memory module (DIMM).
5. The memory device of claim 1 , wherein the one or more memories include at least one non-volatile memory.
6. The memory device of claim 1 , wherein the memory device is a non-volatile dual in-line memory module (NVDIMM).
7. A memory module, comprising:
a plurality of volatile memories configured to receive a first reference clock signal from a connected host;
circuitry configured to generate a second reference clock signal;
circuitry configured to compare the first and second reference clock signals to determine the frequency of the first reference clock signal;
circuitry configured to store the determined frequency; and
circuitry configured to adjust one or more voltages of the memory device in response to the stored frequency of the first reference clock signal.
8. The memory module of claim 7 , wherein the circuitry configured to compare the first and second reference clock signals includes:
circuitry configured to count edges of the first reference clock signal over a predetermined number of cycles of the second reference clock signal.
9. The memory module of claim 7 , wherein the memory module is a dual in-line memory module (DIMM).
10. The memory module of claim 7 , wherein the memory module is a non-volatile dual in-line memory module (NVDIMM).
11. A method of operating a memory device, comprising:
receiving, from a connected host, a first reference clock signal;
comparing the first reference clock signal to a second reference clock signal of a predetermined second frequency to determine a first frequency of the first reference clock signal;
storing the determined frequency; and
adjusting one or more voltages of the memory device in response to the stored first frequency of the first reference clock signal.
12. The method of claim 11 , wherein the comparing the first reference clock signal to the second reference clock signal to includes:
counting edges of the first reference clock signal over a predetermined number of cycles of the second reference clock signal.
13. The method of claim 11 , wherein the memory device does not receive an indication of the frequency of the first reference clock signal from the connected host.
14. The memory device of claim 1 , wherein the circuitry configured to store the determined frequency comprises one or more registers, tables, and/or pointers.
15. The memory module of claim 7 , wherein the circuitry configured to store the determined frequency comprises one or more registers, tables, and/or pointers.
16. The method of claim 11 , wherein storing the determined frequency comprises writing the determined frequency to one or more registers, tables, and/or pointers of the memory device.