Multistage development workflow for generating a custom instruction set reconfigurable processor
View Patent ↗Systems and methods which implement workflows for providing reconfigurable processor core algorithms operable with associated capabilities using description files, thereby facilitating the development and generation of instruction sets for use with reconfigurable processors, are shown. Embodiments implement a multistage workflow in which program code is parsed into custom instructions and corresponding capability descriptions for generating reconfigurable processor loadable instruction sets. The multistage workflow of embodiments includes a hybrid threading complier operable to compile input program code into custom instructions using a hardware timing agnostic approach. A timing manager of the multistage workflow of embodiments utilizes capabilities information provided in association with the custom instructions generated by the hybrid threading complier to impose hardware timing on the custom instructions. A framework generator and hardware description language complier are also included in the multistage workflow of embodiments.
1. A method for generating an instruction set for a field-programmable gate array (FPGA) reconfigurable processor implementation, the method comprising:
accepting input of a set of custom instructions that together provide a reconfigurable processor core algorithm for the FPGA reconfigurable processor instruction set;
analyzing capabilities implicated by custom instructions of the set of custom instructions;
generating a plurality of executable modules comprising routines that provide the capabilities, wherein modules of the plurality of executable modules interact through module interfaces specified by the capabilities, wherein the routines call respective custom instructions and implement threads to perform desired computational operations of corresponding FPGA reconfigurable processor capabilities, and wherein a single custom instruction of the set of custom instructions is executed for an individual thread at any one point in time by an executable module of the plurality of executable modules; and
outputting a framework file comprising a FPGA reconfigurable processor personality formed from the plurality of executable modules, wherein the framework file is an executable description of the reconfigurable processor core algorithm.
2. The method of claim 1 , wherein the framework file is clock cycle accurate with respect to the FPGA reconfigurable processor implementation.
3. The method of claim 2 , wherein the framework file comprises a SystemC model of the FPGA reconfigurable processor.
4. The method of claim 1 , further comprising:
simulating operation of the FPGA reconfigurable processor by execution of the framework file by a processor-based system.
5. The method of claim 4 , further comprising:
optimizing custom instructions of the custom instruction set based on simulated operation of the FPGA reconfigurable processor using the framework file.
6. The method of claim 1 , further comprising:
generating bitstream files for each executable module of the plurality of executable modules from the framework file.
7. The method of claim 6 , wherein the bitstream files are loadable in the FPGA reconfigurable processor for implementing the reconfigurable processor core algorithm.
8. A method for generating an instruction set for a field-programmable gate array (FPGA) reconfigurable processor implementation, the method comprising:
accepting input of a set of custom instructions that together provide a reconfigurable processor core algorithm for the FPGA reconfigurable processor instruction set;
analyzing capabilities implicated by custom instructions of the set of custom instructions;
generating a plurality of executable modules comprising routines that provide the capabilities, wherein modules of the plurality of executable modules interact through module interfaces specified by the capabilities, wherein the routines call respective custom instructions and implement threads to perform desired computational operations of corresponding FPGA reconfigurable processor capabilities, and wherein a single custom instruction of the set of custom instructions is executed for an individual thread at any one point in time by an executable module of the plurality of executable modules;
outputting a framework file comprising a FPGA reconfigurable processor personality formed from the plurality of executable modules, wherein the framework file is an executable description of the reconfigurable processor core algorithm, and wherein the framework file is clock cycle accurate with respect to the FPGA reconfigurable processor implementation;
generating bitstream files for each executable module of the plurality of executable modules from the framework file, wherein the bitstream files are loadable in the FPGA reconfigurable processor for implementing the reconfigurable processor core algorithm.
9. The method of claim 8 , wherein the framework file comprises a SystemC model of the FPGA reconfigurable processor.
10. The method of claim 8 , further comprising:
simulating, prior to generating the bitstream files, operation of the FPGA reconfigurable processor by execution of the framework file by a processor-based system.
11. The method of claim 10 , further comprising:
optimizing, prior to generating the bitstream files, custom instructions of the custom instruction set based on simulated operation of the FPGA reconfigurable processor using the framework file.