Periphery fill and localized capacitance
Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to provide capacitance rather than to operate as memory cells. For example, a memory cell having one or two transistors, or other switching components, and one capacitor, such as a ferroelectric or dielectric capacitor, may be electrically isolated from one or more containers sharing a common access line, and the isolated containers may be used as capacitors. The capacitors may be used for filtering in some examples. Or the capacitance may be used to boost or regulate voltage in, for example, support circuitry.
1. A memory device, comprising:
an array of memory cells that is coupled with a first access line;
a plurality of capacitors each coupled with a plurality of segments of the first access line and each isolated from each memory cell of the array of memory cells; and
circuitry coupled to the array of memory cells and the plurality of capacitors, wherein the array of memory cells and the plurality of capacitors overlie the circuitry.
2. The memory device of claim 1 , wherein each capacitor of the plurality of capacitors is coupled with one of the plurality of segments of the first access line via a first switching component and each memory cell of the array of memory cells comprises a second switching component.
3. The memory device of claim 2 , wherein each of the first switching component and the second switching component comprises a thin-film transistor (TFT).
4. The memory device of claim 3 , wherein a gate of each TFT coupled between one of the plurality of capacitors and the first access line is hardwired to a voltage source.
5. The memory device of claim 1 , wherein each capacitor of the plurality of capacitors is formed in a same container type as each memory cell of the array of memory cells.
6. The memory device of claim 1 , wherein at least one memory cell of the array of memory cells and each capacitor of the plurality of capacitors is coupled with a second access line.
7. The memory device of claim 6 , wherein each memory cell coupled with the second access line comprises a memory element, a first transistor, and a second transistor, and wherein each memory element is in electronic communication with a first segment of the first access line via the first transistor and a second segment of the second access line via the second transistor.
8. The memory device of claim 1 , wherein each memory cell comprises at least one memory element and each memory element of the array of memory cells comprises a ferroelectric capacitor or a dielectric capacitor.
9. The memory device of claim 1 , wherein each of the plurality of capacitors comprises a ferroelectric capacitor or a dielectric capacitor.
10. An apparatus, comprising:
a memory cell that comprises a memory element coupled with a selector device that is coupled with a first access line segment, and wherein the memory element is coupled with a second access line segment, the memory cell formed in a container type common to the memory cell;
a capacitor formed in the container type common to the memory cell and electrically isolated from the memory cell, wherein the capacitor is coupled with a third access line segment and a fourth access line segment; and
a plurality of additional capacitors each formed in the container type common to the memory cell and electrically isolated from the memory cell, wherein each capacitor of the plurality of additional capacitors is coupled with a respective access line segment that is colinear with the first access line segment and the third access line segment.
11. The apparatus of claim 10 , wherein each of the plurality of additional capacitors is coupled with the respective access line segment via a respective transistor.
12. The apparatus of claim 11 , wherein each capacitor of the plurality of additional capacitors is configured to store a charge independent from each other capacitor of the plurality of additional capacitors, and wherein each of the respective transistors is independently controllable.
13. The apparatus of claim 10 , wherein the first access line segment and the third access line segment are formed from a common access line.
14. The apparatus of claim 10 , wherein the memory cell comprises a ferroelectric memory cell, and wherein the capacitor comprises a linear capacitor.