Devices, systems, and methods to synchronize simultaneous DMA parallel processing of a single data stream by multiple devices
View Patent ↗Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.
1. An electronic device, comprising:
a plurality of pattern-recognition processors, wherein each pattern-recognition processor of the plurality of pattern-recognition processors comprises a plurality of programmable elements, wherein each programmable element of the plurality of programmable elements comprises a plurality of memory cells configured to be selectively utilized in an analysis of data;
a control bus coupled to each pattern-recognition processor of the plurality of pattern-recognition processors, wherein the control bus is configured to transmit a control signal to a first pattern-recognition processor of the plurality of pattern-recognition processors to control movement of the data from a data stream into and out of the first pattern-recognition processor; and
a pattern-recognition cluster comprising the plurality of pattern-recognition processors and the control bus, wherein the pattern-recognition cluster is configured to request control of a data bus configured to provide the data stream from a CPU coupled to the pattern-recognition cluster.
2. The electronic device of claim 1 , wherein the control bus is configured to transmit the control signal to a second pattern-recognition processor of the plurality of pattern-recognition processors to control movement of the data from the data stream into and out of the second pattern-recognition processor.
3. The electronic device of claim 2 , wherein the control bus is configured to transmit the control signal to the first pattern-recognition processor and to the second pattern-recognition processor concurrently.
4. The electronic device of claim 3 , wherein the first pattern-recognition processor and the second pattern-recognition processor operate concurrently on received data in response to the control signal.
5. The electronic device of claim 1 , wherein the pattern-recognition cluster is configured to yield control of the data bus to the CPU.
6. The electronic device of claim 5 , wherein the pattern-recognition cluster is configured to notify the CPU upon completion of the analysis of the data stream.
7. The electronic device of claim 6 , wherein the pattern-recognition cluster is configured to yield control of the data bus to the CPU upon completion of the analysis of the data stream.
8. A system, comprising:
a processing unit adapted to generate information related to processing of a data stream; and
a pattern-recognition cluster comprising:
a plurality of pattern-recognition processors, wherein each pattern-recognition processor of the plurality of pattern-recognition processors comprises a plurality of programmable elements, wherein each programmable element of the plurality of programmable elements comprises a plurality of memory cells configured to be selectively utilized in an analysis of data;
a control bus coupled to each pattern-recognition processor of the plurality of pattern-recognition processors, wherein the control bus is configured to transmit a control signal to a first pattern-recognition processor of the plurality of pattern-recognition processors to control movement of data from the data stream into and out of the first pattern-recognition processor; and
a data bus configured to provide the data stream to the pattern-recognition cluster, wherein the pattern-recognition cluster is configured to request control of the data bus from the processing unit.
9. The system of claim 8 , wherein the control bus is configured to transmit the control signal to a second pattern-recognition processor of the plurality of pattern-recognition processors to control movement of data from the data stream into and out of the second pattern-recognition processor.
10. The system of claim 9 , wherein the control bus is configured to transmit the control signal to the first pattern-recognition processor and to the second pattern-recognition processor currently.
11. The system of claim 10 , wherein the first pattern-recognition processor and the second pattern-recognition processor operate concurrently on received data in response to the control signal.
12. The system of claim 8 , wherein the pattern-recognition cluster is configured to yield control of the data bus to the processing unit upon completion of the analysis of the data stream.