Apparatuses and methods for selective row refreshes
Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.
1. A DRAM comprising:
an array of a plurality of DRAM memory cells including a first plurality of DRAM memory cells, and a second plurality of DRAM memory cells, the second plurality of DRAM memory cells being physically proximate to the first plurality of DRAM memory cells;
a word line driver configured to activate the first plurality of DRAM memory cells responsive, at least in part, to receiving a first row-address and activate the second plurality of DRAM memory cells responsive, at least in part, to receiving a second row-address; and
a circuit coupled to the word line driver,
wherein the circuit is configured to:
provide the word line driver with the first row-address;
latch the first row-address;
generate the second row-address responsive, at least in part, to latching the first row-address; and
provide the word line driver with the second row-address responsive, at least in part, to determining that a number of refresh operations have occurred, and
wherein each of the refresh operations includes reading data out of a corresponding plurality of DRAM memory cells of the array of a plurality of DRAM memory cells and subsequently writing the data back to the corresponding plurality of DRAM memory cells of the array of a plurality of DRAM memory cells.
2. The DRAM of claim 1 , wherein the circuit comprises a refresh counter configured to generate a third row-address, and provide the third row-address to the word line driver responsive, at least in part, to a refresh command.
3. The DRAM of claim 2 , wherein the circuit comprises a refresh control circuit configured to determine that a number of refresh operations have occurred by receiving the third row-address.
4. The DRAM of claim 3 , wherein the refresh control circuit is configured to determine that a number of refresh operations have occurred by determining that a particular bit of the third row-address has transitioned from a first state to a second state.
5. The DRAM of claim 3 , wherein the refresh control circuit is further configured to assert a control signal to the refresh counter, responsive, at least in part, to the refresh command, wherein the refresh counter is configured to increment the third row-address, based, at least in part, on the control signal.
6. The DRAM of claim 5 , wherein the refresh counter is further configured to resume providing the third row-address during an operation that the second row-address is provided to the word line driver.
7. The DRAM of claim 2 , wherein the refresh counter comprises a binary counter.
8. The DRAM of claim 1 , further comprising an address latch circuit configured to latch the first row-address externally generated.
9. The DRAM of claim 8 , wherein the circuit is further configured to selectively provide the second row-address to the word line driver when interrupts to provide the first row-address and a third row-address to the word line driver.
10. A DRAM comprising:
an array of a plurality of DRAM memory cells including a first plurality of DRAM memory cells, and a second plurality of DRAM memory cells, the second plurality of DRAM memory cells being physically adjacent to the first plurality of DRAM memory cells;
a word line driver configured to activate the first plurality of DRAM memory cells responsive, at least in part, to receiving a first row-address and activate the second plurality of DRAM memory cells responsive, at least in part, to receiving a second row-address; and
a circuit coupled to the word line driver,
wherein the circuit is configured to:
provide the word line driver with the first row-address;
latch the first row-address;
generate the second row-address responsive, at least in part, to latching the first row-address; and
provide the word line driver with the second row-address responsive, at least in part, to determining that a number of refresh operations have occurred, and
wherein each of the refresh operations includes reading data out of a corresponding plurality of DRAM memory cells of the array of a plurality of DRAM memory cells and subsequently writing the data back to the corresponding plurality of DRAM memory cells of the array of a plurality of DRAM memory cells.
11. The DRAM of claim 10 , wherein the circuit comprises a refresh counter configured to generate a third row-address, and provide the third row-address to the word line driver responsive, at least in part, to a refresh command.
12. The DRAM of claim 11 , wherein the circuit comprises a refresh control circuit configured to determine that a number of refresh operations have occurred by receiving the third row-address.
13. The DRAM of claim 12 , wherein the refresh control circuit is configured to determine that a number of refresh operations have occurred by determining that a particular bit of the third row-address has transitioned from a first state to a second state.
14. The DRAM of claim 12 , wherein the refresh control circuit is further configured to assert a control signal to the refresh counter, responsive, at least in part, to the refresh command, wherein the refresh counter is configured to increment the third row-address, based, at least in part, on the control signal.
15. The DRAM of claim 14 , wherein the refresh counter is further configured to resume providing the third row-address during an operation that the second row-address is provided to the word line driver.
16. The DRAM of claim 11 , wherein the refresh counter comprises a binary counter.
17. The DRAM of claim 10 , further comprising an address latch circuit configured to latch the first row-address externally generated.
18. The DRAM of claim 17 , wherein the circuit is further configured to selectively provide the second row-address to the word line driver when interrupts to provide the first row-address and a third row-address to the word line driver.
19. A DRAM comprising:
an array of a plurality of DRAM memory cells including a first plurality of DRAM memory cells, the array further including a second plurality of DRAM memory cells adjacent to the first plurality of DRAM memory cells; and
a word line driver configured to:
activate the first plurality of DRAM memory cells responsive, at least in part, to receiving a first row-address, and
activate the second plurality of DRAM memory cells responsive, at least in part, to receiving a second row-address when a number of refresh operations have occurred,
wherein each of the refresh operations includes reading data out of a corresponding plurality of DRAM memory cells of the array and subsequently writing the data back to the corresponding plurality of DRAM memory cells of the array.