Apparatuses and methods for selective row refreshes
View Patent ↗Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.
1. An apparatus, comprising:
a refresh control circuit configured to receive a target address associated with a target plurality of memory cells from an address bus, the refresh control circuit further configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred,
wherein a plurality of memory cells associated with the proximate address comprise a plurality of memory cells proximate the target plurality of memory cells.
2. The apparatus of claim 1 , wherein the proximate address is a first proximate address and the plurality of memory cells proximate the target plurality of memory cells is a first plurality of memory cells adjacent the target plurality of memory cells,
wherein the refresh control circuit is further configured to provide a second proximate address to the address bus,
wherein the second proximate address is associated with a second plurality of memory cells adjacent the target plurality of memory cells different from the first plurality of memory cells adjacent the target plurality of memory cells.
3. The apparatus of claim 2 , wherein the refresh control circuit is further configured to provide the second proximate address to the address bus responsive, at least in part, to performing an exclusive OR operation on the target address and the first proximate address.
4. The apparatus of claim 1 , wherein the refresh control circuit is further configured to determine that the number of refresh operations have occurred based, at least in part, on a bit of a refresh address.
5. The apparatus of claim 1 , wherein the refresh control circuit is further configured to determine whether the plurality of memory cells proximate the target plurality of memory cells is functional.
6. The apparatus of claim 1 , wherein the refresh control circuit is further configured to latch the target address responsive, at least in part, to an active command.
7. The apparatus of claim 1 , wherein the apparatus is included in a memory.
8. An apparatus, comprising:
an address bus;
a multiplexer coupled to the address bus and configured to provide a target address to the address bus in association with an operation of a first type, to provide a refresh address to the address bus in association with an operation of a second type, and to provide a proximate address in association with an operation of a third type; and
a refresh control circuit configured to receive the target address from the address bus in association with the operation of the first type, the refresh control circuit further configured to provide the proximate address to the multiplexer in association with the operation of the third type, the proximate address based at least in part, on the target address.
9. The apparatus of claim 8 , wherein the operation of the first type comprises at least one of a read operation or a write operation, and the operation of a second type comprises a refresh operation.
10. The apparatus of claim 9 , wherein the operation of the third type comprises an interrupt operation.
11. The apparatus of claim 8 , wherein the operation of a third type is a first operation of the third type and the proximate address is a first proximate address, the refresh control circuit configured to provide a second proximate address in association with a second operation of the third type.
12. The apparatus of claim 11 , wherein the first and second proximate addresses are associated with respective pluralities of memory cells adjacent a target plurality of memory cells associated with the target address and wherein the refresh control circuit is further configured to provide the first and second proximate addresses to the multiplexer responsive to successive refresh commands.
13. The apparatus of claim 8 , wherein the refresh control circuit is further configured to provide a control signal to the multiplexer, the multiplexer configured to selectively provide the target address to the address bus in association with the operation of a first type, selectively provide the refresh address to the address bus in association with the operation of the second type, and selectively provide the proximate address in association with the operation of the third type based, at least in part, on the control signal.
14. An apparatus, comprising:
a refresh counter configured to provide a refresh address; and
a refresh control circuit coupled to the refresh counter and configured to receive the refresh address and latch a target address, the refresh control circuit further configured to provide a proximate address responsive, at least in part, to determining a bit of the refresh address has a particular state,
wherein the target address is associated with a first plurality of memory cells and the proximate address is associated with a second plurality of memory cells adjacent the first plurality of memory cells.
15. The apparatus of claim 14 , wherein the refresh control circuit is further configured to provide the proximate address responsive, at least in part, to a refresh command.
16. The apparatus of claim 14 , wherein the refresh control circuit is further configured to latch the target address responsive, at least in part, to an active command.
17. The apparatus of claim 14 , wherein the target address comprises a most recent target address provided by a row decoder.
18. The apparatus of claim 14 , wherein the refresh control circuit comprises:
an address control circuit configured to receive the target address and provide proximate address based, at least in pan, on the target address;
an alternate refresh control circuit configured to receive the refresh address and a first control signal, the alternate refresh control circuit further configured to assert a second control signal in association with read and write operations and refresh operations; and
a logic gate configured to receive the second control signal from the alternate refresh control circuit and assert a third control signal to control a refresh counter to hold the value of the refresh address.
19. The apparatus of claim 18 , wherein the alternate refresh control circuit comprises:
a pulse generator configured to receive the refresh address and provide a pulse responsive to determining that a number of refresh operations have been performed;
first and second flip flops configured to be clocked by the first control signal and the second flip flop configured to provide an output signal responsive to the first control signal;
a latch configured to receive the pulse and the output signal and provide the second control signal; and
selection logic configured to receive the second control signal and provide a fourth control signal to the multiplexer.
20. A method, comprising:
selectively providing a target address associated with a target plurality of memory cells to an address bus;
latching the target address; and
selectively providing a proximate address associated with a plurality of memory cells adjacent the target plurality of memory cells to the address bus responsive, at least in part, to determining a particular number of refresh operations have occurred.
21. The method of claim 20 , wherein determining a particular number of refresh operations have occurred comprises determining a state of a bit of a refresh address.
22. The method of claim 20 , further comprising:
selectively providing a refresh address to the address bus; and
incrementing the refresh address.
23. The method of claim 20 , wherein providing the proximate address associated with a plurality of memory cells adjacent the target plurality of memory cells comprises incrementing the target address.
24. A method, comprising:
latching a target address associated with a target plurality of memory cells;
generating a plurality of proximate addresses based, at least in part, on the target address, each of the plurality of proximate addresses associated with a respective plurality of memory cells adjacent the target plurality of memory cells;
determining whether a number of refresh operations have occurred; and
if the number of refresh operations have occurred, providing each of the plurality of proximate addresses to an address bus responsive, at least in part, to respective refresh commands.
25. The method of claim 24 , wherein determining whether a number of refresh operations have occurred comprises:
receiving a refresh address; and
providing a pulse responsive, at least in part, to a bit of the refresh address transitioning from a first state to a second state.
26. The method of claim 24 , wherein providing each of the plurality of proximate address to an address bus responsive, at least in part, to respective refresh commands comprises not asserting a count control signal.