Apparatuses and methods for configurable command and data input circuits for semiconductor memories

1. An apparatus, comprising:

a command decoder configured to receive command signals and provide internal control signals to cause an operation to be performed, wherein the operation to be performed includes at least a read operation and a write operation; and

a clock blocking circuit, the clock block circuit configured to receive a first progress signal indicative of a read operation in progress, a second progress signal indicative of a write operation in progress, and a clock signal, the clock blocking circuit configured to provide an active read clock signal, an active write clock signal, and an active common clock signal responsive to an active clock signal when the first and second progress signals indicate neither a write nor read operation is in progress, and further configured to provide the active read and active common clock signals and an inactive write clock signal when the first progress signal indicates a read operation in progress and to provide the active write and active common clock signals and an inactive read clock signal when the second progress signal indicates a write operation is in progress.

2. The apparatus of claim 1 , wherein the clock blocking circuit comprises:

write clock logic configured to receive the clock signal and provide an active write clock signal responsive to an active clock signal and the second progress signal indicating a write operation in progress and to provide an inactive write clock signal responsive to an active clock signal and the first progress signal indicating a read operation in progress;

common clock logic configured to receive the clock signal and provide an active common clock signal responsive to an active clock signal; and

read clock logic configured to receive the clock signal and provide an active read clock signal responsive to an active clock signal and the first progress signal indicating a read operation in progress and to provide an inactive read clock signal responsive to an active clock signal and the second progress signal indicating a write operation in progress.

3. The apparatus of claim 2 , further comprising:

AND logic configured to receive the first and second progress signals and configured to provide a control signal indicative of both the read and write operations in progress;

write clock control logic configured to receive the first progress signal and the control signal from the AND logic and configured to provide a write clock control signal to the write clock logic to control provision of an active write clock signal or an inactive write clock signal based on the first progress signal and the control signal from the AND logic; and

read clock control logic configured to receive the second progress signal and the control signal from the AND logic and configured to provide a read clock control signal to the read clock logic to control provision of an active read clock signal or an inactive read clock signal based on the second progress signal and the control signal from the AND logic.

4. The apparatus of claim 3 , wherein the write clock control logic includes a delay circuit configured to provide a delay to the first progress signal and control a delay time between when the first progress signal changes to indicate a read operation in progress and when the write clock control logic provides the write clock control signal to control the write clock logic to provide an inactive write clock signal while receiving the active clock signal.

5. The apparatus of claim 2 , wherein the clock blocking circuit is further configured to provide the active read, active write, and active common clock signals when the first and second progress signals indicate both a read operation and write operation are in progress.

6. The apparatus of claim 2 , further comprising:

a first control circuit configured to provide a control signal indicative of both the read and write operations in progress;

a second control circuit configured to provide a write clock control signal to the write clock logic based on the first progress signal and the control signal; and

a third control circuit configured to provide a read clock control signal to the read clock logic based on the second progress signal and the control signal from the AND logic.

7. The apparatus of claim 6 , wherein the second control circuit is further configured to control provision by the write clock logic of an active write clock signal or an inactive write clock signal.

8. The apparatus of claim 6 , wherein the third control circuit is further configured to control provision by the read clock logic of an active read clock signal or an inactive read clock signal.

9. The apparatus of claim 1 , wherein the clock blocking circuit comprises:

write clock logic configured to receive the clock signal and provide the inactive write clock signal when the first progress signal indicates a read operation in progress; and

read clock logic configured to receive the clock signal and provide the inactive read clock signal when the second progress signal indicates a write operation in progress.

10. The apparatus of claim 9 , further comprising:

write clock control logic including a delay circuit configured to provide a delay to the first progress signal; and

read clock control logic including a delay circuit configured to provide a delay to the second progress signal.

11. An apparatus, comprising:

a command decoder configured to receive command signals and provide internal control signals to cause an operation to be performed, wherein the operation to be performed includes at least a read operation and a write operation; and

a clock blocking circuit, the clock block circuit configured to receive a read in progress signal, a write in progress signal, and a clock signal, the clock blocking circuit configured to provide an active read clock signal corresponding to the read in progress signal indicating a read operation in progress and to provide an active write clock signal corresponding to the write in progress signal indicating a write operation in progress.

12. The apparatus of claim 11 , wherein the clock blocking circuit comprises:

write clock logic configured to receive the clock signal and provide an active write clock signal responsive to an active clock signal and the write in progress signal indicating a write operation in progress and to provide an inactive write clock signal responsive to an active clock signal and the read in progress signal indicating a read operation in progress.

13. The apparatus of claim 11 , wherein the clock blocking circuit comprises:

common clock logic configured to receive the clock signal and provide an active common clock signal responsive to an active clock signal.

14. The apparatus of claim 11 , wherein the clock blocking circuit comprises:

read clock logic configured to receive the clock signal and provide an active read clock signal responsive to an active clock signal and the read in progress signal indicating a read operation in progress and to provide an inactive read clock signal responsive to an active clock signal and the write in progress signal indicating a write operation in progress.

15. The apparatus of claim 11 , further comprising:

write clock control logic including a delay circuit configured to provide a delay to the read in progress signal and control a delay time between when the read in progress signal changes to indicate a read operation in progress and when the write clock control logic provides a write clock control signal,

wherein the clock blocking circuit further comprises write clock logic configured to provide an inactive write clock signal when the read in progress signal indicates a read operation in progress, while receiving an active clock signal.

16. The apparatus of claim 11 , wherein the clock blocking circuit is further configured to provide an active common clock signal corresponding to either the read in progress signal indicating a read operation in progress or the write in progress signal indicating a write operation in progress, and

wherein the clock blocking circuit is further configured to provide the active read, active write, and active common clock signals when the read in progress signal and the write in progress signal indicate both a read operation and write operation are in progress.

17. An apparatus, comprising:

a command decoder configured to receive command signals and provide internal control signals to cause an operation to be performed, wherein the operation to be performed includes at least a read operation and a write operation; and

a clock blocking circuit, the clock block circuit configured to receive a first progress signal indicative of a read operation in progress, a second progress signal indicative of a write operation in progress, and a clock signal, the clock blocking circuit configured to provide an active read clock signal when the first progress signal indicates a read operation in progress and to provide an active write clock signal when the second progress signal indicates a write operation is in progress.

18. The apparatus of claim 17 , wherein the clock blocking circuit is further configured to provide the active read clock signal, the active write clock signal, and an active common clock signal responsive to an active clock signal when the first and second progress signals indicate neither the write nor read operation is in progress.

19. The apparatus of claim 18 , wherein the clock blocking circuit is further configured to provide the active read and active common clock signals and an inactive write clock signal when the first progress signal indicates the read operation in progress.

20. The apparatus of claim 19 , wherein the clock blocking circuit is further configured to provide the active write and active common clock signals and an inactive read clock signal when the second progress signal indicates the write operation is in progress.