Methods and system with dynamic ECC voltage and frequency
View Patent ↗Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.
1. A storage system comprising:
a memory array; and
a memory controller configured to communicate with a host processor of a host device, wherein the memory controller is programmed to perform operations including:
monitoring at least one parameter related to power level of the host processor; and
dynamically adjusting a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host, device.
2. The storage system of claim 1 , wherein the at least one parameter includes battery level of the host processor.
3. The storage system of claim 1 , wherein the at least one parameter includes bandwidth of the host processor.
4. The storage system of claim 1 , wherein the at least one parameter includes a processing speed demand of the host processor.
5. The storage system of claim 1 , wherein the at least one parameter includes a bit error rate of the storage system.
6. The storage system of claim 1 , wherein the at least one parameter includes an amount of wear of the memory array.
7. The storage system of claim 1 , wherein the at least one parameter includes an environmental condition.
8. The storage system of claim 7 , wherein the environmental condition includes an environmental temperature.
9. The storage system of claim 1 , wherein the memory controller is further programmed to perform operations comprising:
saving a last setting of at least one of a clock frequency and the voltage level of the error-correcting code (ECC) subsystem of the memory controller; and
restoring the last setting when entering or exiting sleep mode for the storage system.
10. A method comprising:
monitoring, by a memory controller, at least one parameter related to power level of a host processor of a host device configured to communicate with the memory controller; and
dynamically adjusting, by the memory controller, a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.
11. The method of claim 10 , further comprising dynamically adjusting a clock frequency of the ECC subsystem including using ring buffers to adjust for clock domain differences for the ECC subsystem.
12. The method of claim 10 , further comprising dynamically adjusting a clock frequency of the ECC subsystem including using glitch-less clocking to support dynamic frequency changes for the ECC subsystem.
13. The method of claim 10 , wherein dynamically adjusting the voltage level of the ECC subsystem includes using glitch-less clocking to support dynamic voltage changes for the ECC subsystem.
14. The method of claim 10 , wherein the ECC subsystem includes a per channel voltage system that supports different voltages for operation of the ECC subsystem on different channels.
15. The method of claim 10 , wherein the ECC subsystem includes a per channel frequency system that supports different frequencies for operation of the ECC subsystem on different channels.
16. The method of claim 10 , wherein the ECC subsystem includes a ECC generation logic and a ECC checking logic, and wherein the ECC generation logic is configured to operate at a different, voltage level than the ECC checking logic.
17. The method of claim 10 , wherein the ECC subsystem includes a ECC generation logic and a ECC checking logic, and wherein the ECC generation logic is configured to operate at a different frequency level than the ECC checking logic.
18. A non-transitory computer readable storage medium comprising instructions thereon that, when executed by a processor, cause the processor to perform operations comprising:
monitoring at least one parameter related to power level of a host processor of a host device configured to communicate with the processor; and
dynamically adjusting a voltage level of an error-correcting code (ECC) subsystem based on the at least one parameter to control power usage of the host device.
19. The computer readable storage medium of claim 18 , wherein the processor is further programmed to perform operations comprising:
saving a last setting of at least one of a clock frequency and the voltage level f the error-correcting code (ECC) subsystem.
20. The computer readable storage medium of claim 19 , wherein the processor is further programmed to perform operations comprising:
restoring the last setting when entering or exiting sleep mode.