Memory device with write data bus control
Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.
1. A method of transmitting a data signal between a first chip and a second chip, the method comprising:
at the first chip:
receiving a data strobe signal;
generating an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal having an active period between a first edge and a second edge;
capturing first data from a set of input terminals responsive, at least in part, to the first edge of the internal strobe signal;
capturing second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal;
providing a control signal responsive, at least in part, to the internal strobe signal, the control signal having an active pulse width longer than the active period of the internal strobe signal; and
providing the first and second data to a set of data terminals coupled to the second chip responsive, at least in part, to the control signal.
2. The method of claim 1 , wherein providing the control signal responsive, at least in part, to the internal strobe signal comprises:
causing a delay corresponding to an additional pulse width to the internal strobe signal at a delay circuit, and
executing a logical OR operation of the internal strobe signal and an output signal of the delay circuit to provide the control signal.
3. The method of claim 1 further comprising:
receiving a first command signal in the first chip; and
providing a command state signal responsive to the first command signal;
wherein generating the internal strobe signal comprises generating the internal strobe signal responsive to the command state signal.
4. The method of claim 1 further comprising:
capturing the first data and the second data in the second chip responsive to a signal based on the internal strobe signal from the first chip; and
providing the first data and the second data responsive to an internal clock signal independent from the signal based on the internal strobe signal.
5. The method of claim 4 further comprises providing the internal clock signal from a first time in the second chip, responsive to a first command signal from the first chip.
6. The method of claim 1 , wherein the first chip and the second chip are stacked via one or more through substrate vias (TSVs).
7. The method of claim 5 further comprising:
in the second chip, providing a command enable signal in an active state from a second time that is a predetermined number of cycles of the internal clock signal after the first time, responsive to the first command signal from the first chip.
8. The method of claim 7 further comprising, in the second chip, activating a buffer to provide the first and second data from a buffer circuit to a read and writing bus responsive, at least in part, to the command enable signal in the active state.
9. The method of claim 7 further comprising, in the second chip:
causing a first delay of the internal clock signal relative to the first command signal; and
causing a second delay of the command enable signal relative to the first command signal.
10. The method of claim 9 , wherein the first delay is an address strobe command latency.
11. The method of claim 9 further comprising, in the second chip:
providing a plurality of latency signals; and
providing a latency sum signal based on the plurality of latency signals;
wherein the internal clock signal has an active period responsive to the latency sum signal.
12. A method of transmitting a data signal between a first chip and a second chip, the first chip and the second chip are stacked via one or more through substrate vias (TSVs), the method comprising:
at the first chip:
receiving a data strobe signal at the first chip;
generating an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal having an active period;
capturing data from a set of input terminals responsive, at least in part, to the internal strobe signal; and
providing a control signal responsive, at least in part, to the internal strobe signal; and
providing the captured data to at least one of the TSVs to the second chip responsive, at least in part, to the control signal; and
at the second chip:
capturing the data responsive to a signal based on the internal strobe signal from the first chip; and
providing the data responsive to an internal clock signal independent from the signal based on the internal strobe signal.
13. The method of claim 12 , wherein the control signal having an active pulse width longer than the active period of the internal strobe signal.
14. The method of claim 12 , wherein providing the control signal responsive, at least in part, to the internal strobe signal comprises:
causing a delay corresponding to an additional pulse width to the internal strobe signal at a delay circuit, and
executing a logical OR operation of the internal strobe signal and an output signal of the delay circuit to provide the control signal.
15. The method of claim 12 further comprising:
receiving a first command signal in the first chip; and
providing a command state signal responsive to the first command signal;
wherein generating the internal strobe signal comprises generating the internal strobe signal responsive to the command state signal.
16. A method of transmitting a data signal between a first chip and a second chip, the first chip and the second chip are stacked via one or more through substrate vias (TSVs), the method comprising:
capturing data in the second chip responsive to a signal based on an internal strobe signal from the first chip;
providing an internal clock signal from a first time, responsive to a first command signal from the first chip;
providing the data responsive to the internal clock signal independent from the signal based on the internal strobe signal; and
providing a command enable signal in an active state from a second time that is a predetermined number of cycles of the internal clock signal after the first time, responsive to the first command signal from the first chip.
17. The method of claim 16 further comprising:
causing a first delay of the internal clock signal relative to the first command signal; and
causing a second delay of the command enable signal relative to the first command signal.
18. The method of claim 17 , wherein the first delay is an address strobe command latency.
19. The method of claim 18 further comprising:
providing a plurality of latency signals; and
providing a latency sum signal based on the plurality of latency signals;
wherein the internal clock signal has an active period responsive to the latency sum signal.
20. The method of claim 16 , wherein the data comprises a first data and a second data, wherein:
the first data is captured in the first chip responsive, at least in part to a first edge of the internal strobe signal; and
the second data is captured in the first chip responsive, at least in part to a second edge of the internal strobe signal.